查询词典 memory cell

The bus having a dual-terminated transmission line that communicatively couples a memory control hub with a memory repeater hub that each have a Rambus ASIC Cell.

该总线具有一条通信连接一个存储器控制集线器和一个存储器中继器集线器的双终端传输线路，其中每一个集线器都具有一个Rambus ASIC Cell。

With the electrical connections at the top and bottom side of the wafer-level IC packaging Lead-frame structure and composition of the surface-mount semiconductor package structure Multi-layer printed circuit board Antifuse and its formation method and with the anti-fuse non-volatile memory device unit cell Tandem electric signal processing circuit and electronic device Light-emitting diode packaging structure and encapsulation method Electronic Packaging Structure Flip-chip high-speed optoelectronic components and structure Pairs of piezoelectric friction side by side to promote the three-step device and scanning probe microscope Light-emitting diode and its manufacturing method, the production base of light-emitting diode method Three or four parallel advance of stepping piezoelectric device and scanning probe microscope lens body Silicon substrate and its manufacturing method Semiconductor device and voltage-divider A polysilicon layer and the microcrystalline silicon layer of the double-substrate active layer structure, methods and devices The edge of the thickness of silicon controlled Of a lateral semiconductor devices and high-voltage devices With a vertical-channel transistors semiconductor device Of a memory array and for the manufacture of a memory array method Read-only memory cell array structure Active-matrix substrate and display device High-voltage semiconductor integrated circuit devices, dielectric isolated type semiconductor device Image sensing devices Lens module and its manufacturing methods Solid-state imaging device and camera Injection angle for the trench isolation Organic Light-Emitting Display Device Organic light-emitting display device Bipolar transistor structure of the surface passivation Double-triggered silicon-controlled rectifier HFET Metal-oxide semiconductor transistors Self-aligned trench accumulation mode field effect transistor structure Thin-film transistors and Display Devices TFT Lead Diode Low-frequency, low noise, low-flashing diode Used for thin-film solar cells trap light structure Transparent sun solar cells Quaternary semiconductor heterojunction photovoltaic cells heat Si nano-pillar array heterojunction thin-film solar cells GaN-based micro-composite solar cells isotope Optical sensor Semiconductor by optical components Imaging Detector Transparent conductive oxide coating Silicon-based high-performance dual-junction solar cells Thin-film solar cells Alien LED Devices

非专业，不在行，求高手帮忙。谢谢！具有顶部及底部侧电连接的晶片级集成电路封装导线架结构及其构成的表面黏着型半导体封装结构多层印刷电路板反熔丝及其形成方法和具有该反熔丝的非易失性存储器件的单位单元串联用电式信号处理电路及电子装置发光二极管的封装结构及其封装方法电子封装结构高速光电组件及其芯片倒装结构双压电体并排推动的三摩擦力步进器与扫描探针显微镜发光二极管及其制作方法、发光二极管的底座的制作方法三或四压电体并行推进的步进器及其扫描探针显微镜镜体硅衬底及其制造方法半导体装置与分压电路具多晶硅层及微晶硅层的双底材主动层结构、方法及装置硅晶片的受控边缘厚度一种半导体横向器件和高压器件具有垂直沟道晶体管的半导体器件一种记忆体阵列及其用于制造一记忆体阵列的方法只读内存单元阵列结构有源矩阵基板和显示装置高耐压半导体集成电路装置、电介质分离型半导体装置图像感测装置透镜模块及其制造方法固态成像装置和照相机用于沟道隔离的斜角注入有机电致发光显示装置有机发光显示装置双极晶体管的表面钝化结构双触发型可控硅整流器异质结场效应晶体管金属氧化物半导体晶体管自对准沟槽累加模式场效应晶体管结构薄膜晶体管及显示器件薄膜晶体管无铅二极管低频、低噪音、低闪烁的二极管用于薄膜太阳电池的陷光结构透明遮阳太阳能电池片四元半导体的异质结热光伏电池硅基纳米柱阵列异质结薄膜太阳能电池氮化镓太阳能同位素复合型微电池光学传感器半导体受光元件成像探测器透明导电氧化物涂层硅基高效双结太阳能电池薄膜太阳能电池异形LED器件

The intrusion detection system is mainly composed of memory cell model, mature cell model and immature cell model.

该系统包括三个主要模块：记忆细胞检测模块、成熟细胞检测模块和未成熟细胞的耐受模块。

As an example, each memory cell in a memory array may have an output to indicate the status of the cell.

例如，存储阵列中的每一存储单元可具有一用于指示该单元的状态的输出。

The page buffer programs data to a selected memory cell or read data from the selected memory cell.

页面缓冲器将数据编程至选择的存储单元，或从选择的存储单元读取数据。

It is because the spending of area and power of the SRAM memory cell takes a lot of percentage of the whole macro modules'. Using the α exponent MOSFET model to result the word line、bit line power model and delay model, together with the area model and analysis of the read/write reliability, we bring out a method to optimize the memory cell and evaluate the performance of the result.

特别对占模块面积和功耗绝大部分比例的SRAM存储单元做了细致的设计和仿真实验，通过采用α指数MOSFET模型推导出SRAM的字线、位线功耗模型和延迟模型，并配合存储单元的面积模型和读写可靠性分析，提出了一种优化存储体单元结构的方法，并对优化前后的性能进行了评估。

During the read operation, which connects a bit line or bit line bar to a memory cell, the charges stored in a memory cell may change the voltage level of the bit line.

在读取作业期间，将一位线或位线棒连接至一存储单元，存储于存储单元中的电荷可改变位线的电压电平。

In one embodiment, a memory device comprises a first memory cell and a second memory cell, wherein the first memory cell comprises a first transistor coupled to a bit line and the second memory cell comprises a second transistor coupled to a bit line bar.

在一实施例中，一种存储装置包含一第一存储单元及一第二存储单元，其中该第一存储单元包含一耦接至一位线的第一晶体管，而该第二存储单元包含一耦接至一位线棒的第二晶体管。

See also Nozaki et al.,"A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application," IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar element in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory element channel to form a separate select transistor.

还参见Nozaki等人的&A1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application&(IEEE Journal of Solid-State Circuits，第26卷，第4期，1991年4月，497-501页)，其描述了处于分裂栅极配置中的类似元件，其中掺杂的多晶硅栅极在存储器元件沟道的一部分上延伸以形成单独的选择晶体管。

The boundary of analytical model and statistical model is clearly divided in this performance model, and evaluation accuracy is improved. Secondly, based on embedded SRAM performance hybrid model, this article adopts bionics algorithm-ant algorithm to optimize hierarchical embedded SRAM structure. This method which adjusts memory system structure improves memory system performance. Finally, considering the factors such as memory cell area, power, delay and reliability, this article establishes static 6-T memory cell area, power, delay and static noise margin equations, analyzes 6-T memory cell device dimension constraints under "read upset" and "write upset", then proposes a method to enhance embedded SRAM performance by optimizing 6-T memory cell size. In order to realize embedded SRAM design and verify proposed optimization methods, this article takes the Garfield202 system chip as the platform, which embeds A720T processor and 20KB Scratch-Pad memory.

首先针对嵌入式SRAM结构，采用多元线性回归方法分析SRAM宏单元性能指标，采用解析方法分析控制电路延时，结合以上这两种方法建立嵌入式SRAM性能混合模型，该模型清晰划分两种建模方法的各自适用范围，提高了模型精度；其次以该混合模型为基础建立存储体性能目标函数，采用仿生优化算法—蚂蚁算法优化嵌入式SRAM结构，使之达到最优设计；最后综合考虑面积、功耗、速度以及可靠性等因素，建立静态6-T存储单元面积、功耗、延时以及静态噪声容限方程，分析了&读破坏&和&写破坏&的晶体管尺寸约束，优化了6-T存储单元尺寸，提高了嵌入式SRAM性能。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失