查询词典 logic level

ET the Framework multilayer skeleton system has designed this system structure, then carries on the demand analysis to the office automation, introduced in this foundation the database design and the programming unit process as well as the page base class, the user register the confirmation the expression level, the service logic level, the data accessing level, the general level four realizations methods.

et Framework多层构架体系设计了本系统的结构，接着对办公自动化进行需求分析，在此基础上介绍了数据库设计和程序设计的基本过程以及页面基类、用户登录验证的表示层、业务逻辑层、数据访问层、通用层四层实现方法。

The inspection unit includes storing unit, logic switching unit and drive change-over switch, inspects whether the storing unit is normal via detecting the edge change, sets the output of abnormal storing unit in certain logic level and performs different logic operations to different logic level setting values.

检验装置包括储存单元、资料切换开关与边缘探测器。其是以边缘变化是否正确来检验储存单元的运作是否正常，并将出现问题的储存单元的输出设定在一固定的逻辑电位上，再对不同逻辑电位设定值使用不同的逻辑运算。

This problem is usually placed on telephone or data concentrator in the discrete logic level converter to solve.

这个问题通常用置于电话或数据集中器中的分立逻辑电平变换器解决。

They still have the relation of certain logic level of structure: deepness is the foundation of the other quality; flexibility and criticalness is a development on the foundation of the deepness; flexibility is with the criticalness mutually combinative, then express the originality; Had thosequality, then express the agility.

它们还具有一定的逻辑层次关系：深刻性是其它思维品质的基础；灵活性和批判性是在深刻性基础上发展出来的；灵活性和批判性相互结合，表现出独创性；具有了这几种思维品质，就表现出了敏捷性。

This paper presents an open VHDL simulation environment OVSE, which includes the modules of compiler, flattener, linker and simulator HSIM to verify the correctness of hierarchical design of digital circuitry at logic level.

开放的VHDL模拟环境OVSE林守勋，郭玉钗，林宗楷（中国科学院计算技术研究所CAD开放研究实验室，北京100080）摘要本文介绍了一个开放的VHDL模拟环境。

The optimal operating speed without considering the response time of the nonlinear material, the least ON to OFF logic-level contrast ratio, and the minimum power for this half adder obtained were 0.91Tbps, 16dB and 436mW, respectively.

研究表明，当忽略介质本身与光场作用的时间延迟时，该半加器优化后的运算速度为0.91 Tbps，最小消光比为16 dB，最小消耗功率为436 mW。

Chapter 2 introduces power estimation method in logic level, RTL level and behavioral level.

第二章研究了逻辑级、RTL级和行为级估计功耗的方法。

The low power design example applied in a real design is given out in logic level and the circuit level.

在逻辑级、电路级列举了实际设计中考虑到降低系统功耗以后的例子。

The algorithm combines the simulated annealing algorithm with ratio-cut method to ascertain the level of the multi-level multi-way partitioning. Considering the number of cut lines while partitions CLB into cluster, it achieves a better partition result and improve the usage in HFPGA, then optimize the FPGA performance.

该算法将模拟退火算法与ratio-cut思想结合，确定多层多划分的规模后，采用数据结构进行多分优化，在将可配置逻辑块(configurable logic block， CLB)划分到各个簇的时候考虑割线数的目标函数，实现了更好的划分结果，提高了FPGA芯片的利用率，优化了整个芯片的性能。

In logic level, the application of the binary decision diagrams, Markov Chain and boolean difference in power estimation is introduced first, the strategy about how to make a balance between estimation accuracy and estimation velocity is introduced secondly, after that, the new problems emerged in the power estimation of the sequential circuit and the resolution is given out, the power estimation method based on the logic simulation is introduced at last.

在逻辑级功耗估计方法中，首先介绍了二叉判决图、马尔可夫链、布尔差分在功耗估计中的使用，其次研究了功耗估计速度和精度之间进行折衷的方法，然后介绍了时序电路功耗估计中出现的问题以及解决方法，最后介绍了基于逻辑模拟的功耗估计方法。

The absorption and distribution of chromium were studied in ryeusing nutrient culture technique and pot experiment.

采用不同浓度K2CrO4(0，0.4，0.8和1.2 mmol/L)的Hoagland营养液处理黑麦幼苗，测定铬在黑麦体内的亚细胞分布、铬化学形态及不同部位的积累。

By analyzing theory foundation of mathematical morphology in the digital image processing, researching morphology arithmetic of the binary Image, discussing two basic forms for the least structure element: dilation and erosion.

通过分析数学形态学在图像中的理论基础，研究二值图像的形态分析算法，探讨最小结构元素的两种基本形态：膨胀和腐蚀；分析了数学形态学复杂算法的基本原理，把数学形态学的部分并行处理理念引入到家实际应用中。