查询词典 interface routine

It is most likely that only a part of the karst caves could be detected if the boundary of the karsts cave has a certain horizontal extension respectively to measurement layout, but the interface of the karsts caves is not completely smooth plane, and its normal direction is not perpendicular to the tunnel axis. However, the precision of the cave detection is related to interface wave impedance difference of the karst caves, groundwater detection, operator's data acquisition experience and data processing level and so on.

如果溶洞的边界相对于TSP测量布线有一定的横向延伸性，其边界面不一定是完全平滑的表面，但其法线方向与隧道轴线不完全垂直，这类溶洞有可能被部分探测，但探测精度还与溶洞界面两侧的波阻抗差、对地下水的探测、操作人员的数据采集经验和数据处理水平等有关。

We provide you with the following high-quality components, you need to improve the reliability of the equipment: signal isolation / transmitter, relay / optocoupler, lightning / surge protector, switching power supply, with a total Line interface, filter / anti-modules, industrial connectors, sensor / actuator interface module, printed circuit board connector, on-site joint boxes, terminals, the button / indicator light, control / Bus cables and other products.

我们为您提供下述的高品质元器件，以提升您所需设备的高可靠性：信号隔离/变送器、继电器/光电耦合器、防雷/浪涌保护器、开关电源、总线接口、滤波器/抗干扰模块、工业用接插件、传感器/执行器接口单元、印刷电路板接插件、现场接线箱、接线端子、按扭/指示灯、控制/总线电缆等产品。

Interface; intermediate layer; mesosphere; interface layer; interlayer

层内温度随高度的增加而递减。

The interface between oxide film and substrate is distinctive, but there is no obvious interface between electrolytic coloring film and oxide film, which indicates that coloring metal is deposited in micropores.

图纹处氧化膜较厚，无图纹部分较薄，氧化膜与基体界面分明，而电解着色膜与氧化膜无明显的分界面，说明着色金属是沉积在多孔层微孔内。

The card interface in used to collect the personal information from the user's name card. The name card that contains a RFID Tag is read by a RFID reader. The mirror interface is constructed by hiding a minicam in the back of a mirror.

首先，资料的收集方式称为&Card Interface&，将记载个人资料位址的RFID Tag贴在自己的名片上，在收到对方的名片时使用RFID Reader来读取RFID Tag，这个方式使的两个人在初次见面交换名片时也能交换彼此的个人资料，并建立个人所属的资料档案。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

After nail implanted and in the case of compression load, the highest effective stress occurred in the screw hole of nail (nail-screw interface) for comminuted tibial fracture. While as a complete simple fracture the highest stress presented in the outer screw-cortical bone interface.

在最大生理负载下时，一体成型的骨钉最大有效应力发生在骨折处的骨钉上，新设计的分节式骨钉则发生在骨折区域邻近处两节间的界面。

In this paper, we analyze the system integration techniques of HCCADS in details, design a general user interface worktop by using typical interface component sets and present a management strategy that take different methods to manipulate the different engineering data accordingly so that data flow fluently between application system and support software.

对系统集成的相关技术进行了详细的分析，设计了由典型界面部件集及其接口函数组成的通用用户平台；并对应用系统的工程数据管理提出不同的存贮管理策略，保证了应用系统与支撑软件之间的数据畅通。

The article aims to study the interface shearing force regularity of the steel and concrete composite beams with cold formed steel U section with a new method to build calculation formulas of interface shearing force with symmetrical concentrated loads and uniformly distributed load.

目的 采用一种新方法建立冷弯U型钢与混凝土组合梁的界面剪力计算公式，研究冷弯U型钢与混凝土界面剪力分布规律。

Listen,point and check your answers.

听，指出并且检查你的答案。

Warming needle is one of effective treatment methods for knee arthralgia aggravated by cold,and it is simple,safety,so it should be developed in clinical acupuncture and moxibustion extensively.

但以本院科针灸门诊在2005年1月—2006年6月期间共收治膝痛患者100余例，经过临床的诊断后，其中施以温针治疗的48例，疗效显著，报道如下。1临床资料本组病例48