查询词典 instruction address

The pre-decoder compares the BTA with the branch instruction address to determine whether the target and instruction are in the same memory page.

所述预解码器将BTA与转移指令地址进行比较，以确定目标与指令是否位于相同的存储器页内。

Thus, whenever a branch instruction is encountered the disassembly continues simultaneously at both the address following the branch instruction and the address that is the target of the branch instruction.

因此，无论何时遇到一个分支指令，就同时从两个地址继续反汇编：分支指令后面的地址和分支指令的目标地址。

The idea of Autonomous Instruction Memory is to combine Top-Level Instruction Memory and Branch Target Buffer. This kind of architecture has an character of self-generating instruction address.

自主指令记忆体的设计的想法在於结合动态分支预测器和最上层的指令记忆体而拥有自行产生指令位址的特性，因而使得CPU可以不用传送指令位址给自主指令记忆体，而达到降低CPU和自主指令记忆体之间指令位址汇流排上传递资料量的目的。

This is silly, because I should still be able to set a breakpoint based on the instruction address.

这是愚蠢的，因为我仍然可以设置的指令地址的一个断点。

Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

基于上述结论，为了尽量消除转移指令对处理器开发指令级并行性能力的影响，进一步提高处理器性能，在详尽分析目前已存在的转移处理策略的特点与局限性的基础上，首次提出了一种新的转移处理策略即基于分类的层次转移处理策略CHBHS(Classification Based Hierarchical Branch Handling Strategy)，它首先通过扩展传统的体系结构，支持多条件码、条件式执行及多分支转移技术，以使编译程序在进行代码生成时可尽量少生成条件转移指令，从而减少静态条件转移指令的数目；其次，基于不同的转移指令的行为不同这一事实，提出了对不同的转移指令采用不同的机制进行处理的思想，即对无条件转移指令和函数调用指令以及条件转移指令的目标地址，采用转移目标缓冲器来预测，对于函数返回指令，采用所提出一种的高效返回地址栈来预测其目标地址，对于大多数循环控制转移指令，采用所提出的Counter Register Stack来将其所可能带来的损失减少为0，对于其他的条件转移指令采用动态预测机制来预测其方向。

The purpose of such concept is to reduce instruction address traffic between CPU and instruction memory to a minimum.

这个概的目的是要将CPU与指记忆体之间的指位址传输到最低。

A need to access the instruction address stream.

产生一个需要访问的指令地址流。

Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units.

能针对一个或多个特定的存储单元调整将该指令地址译码为一个物理地址的过程。

Address 0 is the currently executing instruction. Address -1 was

因为内存是循环的，每条指令都有无穷多个地址。

Also, a Harvard architecture machine has distinct code and data address spaces: instruction address zero is not the same as data address zero.

同时，哈佛架构机拥有不同的代码和数据地址空间：指令的零地址和数据的零地址不是一回事。

However, as the name（read－only memory）implies, CD disks cannot be written onorchanged in any way.

然而，正如其名字所指出的那样，CD盘不能写，也不能用任何方式改变其内容。

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镀锌钢托盘多用于出口，替代木托盘，免薰蒸，符合欧盟、北美各国对出口货物包装材料的法令要求；喷涂钢托盘适用于重载上货架之用，托盘表面根据需要制作成平板状、波纹状及间隔形式，满足不同的使用要求。