查询词典 input characteristics

Thus, the output will always be driven by a single transistor, either P- channel or N-channel. Since they are as closely matched as possible, the output resistance of the gate will always be the same, and signal behavior is therefore more predictable. Fig. 3.4 CMOS NAND gate One of the main problems with CMOS gates is their speed. They cannot operate very quickly, because of their inherent input capacitance. B-series devices help to overcome these 24 Lesson 3 CMOS Logic Circuit 25 limitations to some extent, by providing uniform output current, and by switching output states more rapidly, even if the input signals are changing more slowly. Note that we haven't gone into all of the details of CMOS gate construction here. For example, to avoid damage caused by static electricity, different manufacturers developed a number of input protection circuits to prevent input voltages from becoming too high. [3] However, these protection circuits don't affect the logical behavior of the gates, so we won't go into the details here. New Words and Phrases 1. CMOS abbr.

略语互补金属氧化物半导体(complementary metallic oxide semiconductor)逻辑，逻辑学，逻辑性，推理方法补充的，补足的，互补的电池供电的门电路，逻辑门，闸门，控制栅，大门，通道，门口，入口伏特，环骑，闪避基础的，基本的，主要的基本原则，基本原理增强型金属氧化物半导体场效应晶体管(metallic oxide semiconductor field effect transistor)反相器，反用换流器，变极器来源，水源，消息来源，原始资料，发起者源，源极排水沟，消耗，排水漏极排出，喝干，耗尽排水，流干，耗尽相同的，相配的，匹配的匹配有效地，有力地，事实上，实际上无限的东西无穷大无穷的，无限的，无数的，极大的接地的正向偏置的，正偏的或非 25 2。

Enter a section: writer_ input available computers are commonly used for direct input and can be used by user input, with the floppy disk image scanning input.

不不输入局部：不不输入方法，可用录入机间接不不输入，也可由用户自带软盘不不输入，图像用扫描仪不不输入。

Various now input methods can be found everywhere, the netizen's normally commonly used input method has a lot of, for instance 5, intelligent ABC, to present search dog input method, QQ input method is waited a moment, the netizen is hitting diphthongal to moment often can play wrongly written character and not was aware of, the key word of such misprint is derived, the website that does before me for instance calls a bell to guide net, when having a name for this website, thought of normally the netizen is typing the homophonic of moment cuts a point, the bell guides with leader homophonic, produced me so this stands now, friends can be drawn lessons from.

现在各种各样的输入法比比皆是，通常网民常用的输入法有许多，比如五笔，智能ABC，到现在的搜狗输入法，QQ输入法等等，网民在打连字的时候往往会打错字而没有察觉出来，这样错字的关键字就衍生出来了，比如我之前做的网站叫铃导网，在为这个网站起名字的时候，就想到了通常网民在打字时候的谐音切入点，铃导跟领导谐音，所以就产生了我现在这个站，朋友们可以借鉴一下。

Backsteppnig control is applied to the positioning of ironless linear motor stage in this thesis. The controller design starts from a lower dimension subsystem and design a Lyapunov candidate for it. By choosing some appropriate virtual control input, the stability of the subsystem is guaranteed. Then extend to a larger system and choose a stabilizing control input for the extended Lyapunov candidate. The procedure is repeated until the overall system's actual control input appears, Again, the overall system's stability is guaranteed when the control input is appropriately chosen.

本论主要探讨逆向步进控制器在线性马达轨迹之控制，控制器之设计方式是由后往前一步一步推导，每一步推导的子系统，均满足Lyapunov稳定法则，在由后往前一步一步推导过程中，每往前推导一步，均必须符合最先所假设的条件与设计，直到方程式与系统的控制输入出现关连性，利用所设计之控制输入将系统的非线性问题予以解决，并因满足Lyapunov稳定法则而收敛。

Each device features receiver high input impedance and input hysteresis for increased noise immunity, and input sensitivity of 200 mV over a common-mode input voltage range from C 0.3 V to 5.5 V. When the inputs are open circuited, the outputs are in the high logic state.

每个器件具有增加抗噪声接收器高输入阻抗和输入滞后，以及投入200毫伏以上的共模输入电压范围从C 0.3 V至5.5五，当输入开路时，输出的是高灵敏度逻辑状态。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

The co-channel interference rejection filter for outputting a second input signal by removing co-channel interference from a first input signal; a first post processor for removing interference other than co-channel interference from the second input signal; a second post processor for removing interference other than co-channel interference from the first input signal; and a selection controller for selecting the output of the post processor which has less error by comparing the output of the first post processor with the output of the second post processor.

一种共道干扰消除器及其方法，其中抗共道干扰滤波器从第一输入信号中除去共道干扰并输出第二输入信号，第一后置处理器除去第二输入信号中的非共道干扰，第二后置处理器除去第一输入信号中的非共道干扰，选择控制器比较第一后置处理器和第二后置处理器的输出，从中选择误差较小的后置处理器输出。

An equal cross-section blade was investigated and a finite element model was built parametrically. Geometrical parameters (such as length, width and thickness), material parameters (such as young's modulus and density) and speed of blade were considered as input random variables while the static frequencies and dynamic frequencies were output random variables. Combining the finite element method, response surface method and Monte Carlo method, the statistical properties and cumulative distribution functions of static frequencies and dynamic frequencies were obtained. Probability sensitivities analysis, which combined the slope of the gradient and the width of the scatter range of the random input variables, was applied to quantitatively evaluate the sensitivities of static frequencies and dynamic frequencies with respect to the random variables. The Scatter plots of structural responses with respect to the random input variables were illustrated how to adjust the values of the static frequencies and dynamic frequencies by changing input random variables.

文中以某试验台用汽轮机等直叶片为研究对象，考虑几何参数、材料参数和转速的随机性，通过有限元参数化建模，将确定性有限元方法、响应面方法和Monte-Carlo模拟法相结合，从而获得了叶片静频、动频的统计特性和累积分布函数；同时考虑随机变量的梯度和离散范围对静、动频的影响，通过概率敏感性分析，定量地判断出叶片静、动频对随机输入变量的敏感性；通过绘制叶片静、动频与输入变量的散点图，定量地分析了如何改变随机变量以调整静、动频率的方法。

Based on the return map and the principle of closed vectors, a new method is proposed to extract unstable periodic orbits embedded in chaotic attractors. As examples, the UPOs embedded in chaotic attractors of Logistic, Hénon and Lorenz are extracted respectively by this method. And our results of Skewed Hénon map also be compared with Nusse's. These results suggest that this method is valid for unstable periodic orbits from period one to period infinite of arbitrary dimension chaotic system. The dynamic considerations of spiking and UPO coding for individual neuron and neural system under external periodic and chaotic exciting stimulus also be studied in this dissertation. A lot of spiking phenomena, such as synchronization, period, and chaos appear alternatively with the changing of the stimulus frequency. For the small stimulus frequency the neuron could completely convey the periodic signal in synchronous anti-phase into interspike intervals sequences. For the slow time–scale chaotic input, the output two ISI sequences are reciprocally related to input signals, and their oscillation wave shape in time course can be derived from that of the input signals variation, furthermore, the similar input sequence and order of UPOs, distribution of LES and value of KYD remain in attractors reconstructed from ISI sequences.

发现周期信号在单个神经元传递过程中，随着激励频率的改变，神经元输出的峰峰间期interspike interval时间序列呈现出周期、混沌和准周期的交错变化，特别当外加激励信号频率较低时，周期信号可以通过神经元ISI序列以反相同步的周期运动形式传递下去；同时无论是周期还是混沌激励信号，在神经系统中的传递均与其自身强度和神经元之间的耦合强度的大小密切相关；快变时间尺度的混沌激励信号在耦合的神经系统传递过程中，会造成大量基本信息的丢失；而慢变时间尺度的混沌激励信号在神经系统传递中，它的非线性特征信息，如混沌吸引子、不稳定周期轨道、Lyapunov指数谱和分形维数，会通过系统输出的ISI序列部分地重现出来，如与输入慢变时间尺度的混沌激励信号相比，神经系统输出的ISI序列具有：相似几何形状的混沌吸引子、相近的Lyapunov指数谱和分形维数、局部结构相同的不稳定周期轨道的排列方式。

The dissecting of samples in group2 were difficult. The root of pulmonary artery and ascending aorta failed to be unfolded because fibrous tissue was tough, right and left fibrous trigone were too firm to be solved by hand. Cardiac muscle fibers couldn't be stripped along myofibrillar trajectory since they were prone to break because of their friability.

组2的心脏解剖困难，表现为纤维组织坚韧，游离肺动脉非常困难；徒手无法松解左、右纤维三角，肺动脉和主动脉根部的游离非常困难；心肌纤维坚硬、质脆，解剖时容易断离成碎块，无法沿纤维走行方向剥离。

We have battled against the odds in a province that has become increasingly violent.

我们对在一个争夺日益激烈省的可能性。