查询词典 in parallel with

Compared with traditional numerical methods, the LB method has several important features, including: simplicity in algorithm, easily programming, direct calculation of pressure from a state equation and amenability to simulate all kinds of flow field with complex boundaries, it also has many advantages in the respect of parallel computation because of its regional evolution.

与传统的计算方法相比较，LB方法具有算法简单、编程容易、压力可以通过状态方程直接求解、能够模拟各种复杂边界的流场等优点，并且计算的局域性使其在并行计算方面也具有很大的优势。

Compared with traditional numerical methods such as the FEM, FDM, etc, the LB method has several important features, including: simplicity in algorithm, easily programming, direct calculation of pressure from a state equation and amenability to simulate all kinds of flow field with complex boundaries, it also has much advantage in the respect of parallel computation because of its regional evolution.

与传统的计算方法如FEM、FDM等相比，LB方法具有算法简单、编程容易、压力可以通过状态方程直接求解、能够模拟各种复杂边界的流场等优点，并且计算的局域性使其在并行计算方面也具有很大的优势。

The multi-aspect flow of ancient prose was established in Zhanguo era. Its style was basically fixed in South and North dynasty. That is the prose with loose single sentences and the parallel writing with antithetic sentences.

古代散文的多向流程是战国那个特殊的时代奠定的，在南北朝时散文的文体与风格基本定型，主要是指散行单句式的散体文和骈偶化的骈文。

In this paper, the convergent conditions in sequence or parallel update mode and the sufficient condition with only one global stable state for Hopfield network model with discrete time and continuous states when its neurons' activation function is non-decreasing (not being strictly monotone increasing) are discussed.

主要讨论离散时间连续状态的Hopfield网络模型中当神经元的激活函数为单调增函数时，并行和串行收敛的充分条件以及具有全局惟一稳定点的充分条件。

In Two-Transistor Flyback Converter circuit, a power semiconductor device in Flyback Converting circuit has been replaced by two power semiconductor devices which parallel connected with an ultra-fast diode with soft recovery characteristics. Two-Transistor Flyback Converter can reduce greatly the switching stress of the power switch and does not need to degausser, suitable for high input voltage Switching Power Supply.

反激变换是从Buck-Boost变换演变而来的，将反激变换电路中的单个功率开关管用两个替代，并在每个功率开关管上并联一十箝啦的快恢复二极管而形成的双晶体管反激变换电路，能大大降低功率开关管承受的开关应力，且不需要消磁电路，非常适用于高输入电压的开关电源。

The boundary being in progress first to the concept subleasing to fixes the main body of a book , compares with to renting right ceding to waiting for the close concept to carry out analysis again , lists and then the comparison carrying out concrete analysis in every country to the legislation pattern and legislation reason subleasing behavior, and to the advantages and disadvantages that lower be unlike legislation pattern be subleased to stipulates; After the secondary , the main body of a book emphasizing the character having analysed a leasehold, have set forth the effect and law consequence subleasing a contract under agreement subleases to and subleases to presumptuously situation respectively , have assumed and parallel comparatively detailed analysis , have discussed problem such as often arousing some problem of dispute in subleasing process , how to handling if the building is subleased to if time of middle lessee enjoy the right of preemption and the lessor , the dispute that the lessee and time of lessee produce because of the fitting up responds to and; Final, the main body of a book have pointed out nowadays"s defect and deficiency about the legal system aspect subleasing to , have set forth and the advantage adopting the liberalism legislation pattern, the conclusion, joins the tendentiousness reaching the liberalism pattern ultimately according with a contract of lease of property function effect more having submitted the suggestion and tentative plan stipulating a few"s to perfect current laws.

本文首先对转租的概念进行界定，再与租赁权让与等相近概念进行分析比较，然后列举各国对转租行为的立法模式及立法理由，并对不同立法模式下的转租规定的利弊进行具体分析比较；其次，本文在着重分析了租赁权的性质后，分别阐述了在同意转租和擅自转租情况下转租合同的效力及法律后果，并作了比较详细的比较分析，并探讨了在转租过程中经常引起争议的一些问题，如房屋转租中次承租人是否享有优先购买权及出租人、承租人与次承租人因装修产生的纠纷应如何处理等问题；最后，本文指出了现今关于转租的法律制度方面的缺陷和不足，并阐述了采取自由主义立法模式的优势，最终得出自由主义模式更符合租赁合同的功能作用的倾向性结论，并提出了对完善现行法律规定一些的建议和设想。

By virtue of bifurcation diagrams, Poincaré maps, orbits, time histories and frequency spectrum diagrams, the nonlinear dynamic responses of the generator rotor and hydraulic turbine rotor with coupling faults were analyzed. The results confirmed rich nonlinear motions such as periodic motion and quasi-periods with different values of parallel misalignment and declination. Moreover, the process of rub-impact is so complex that many low frequencies with large amplitude are in the range of

通过分岔图、Poincaré截面图、轴心轨迹图、时域波形图和幅值谱图系统地分析了发电机转子与水轮机转子在耦合故障下非线性动力学响应，发现机组转子系统随不对中平行量和偏角变化存在周期运动和复杂的拟周期，其碰摩过程非常复杂，机组故障特征频率除主要在1倍频外，还在0.3~0.4倍频处存在幅值较大的谐波分量。

WD40 domain, found in a number of eukaryotic proteins that cover a wide variety of functions including adaptor/regulatory modules in signal transduction, pre-mRNA processing and cytoskeleton assembly; typically contains a GH dipeptide 11-24 residues from its N-terminus and the WD dipeptide at its C-terminus and is 40 residues long, hence the name WD40; between GH and WD lies a conserved core; serves as a stable propeller-like platform to which proteins can bind either stably or reversibly; forms a propeller-like structure with several blades where each blade is composed of a four-stranded anti-parallel b-sheet; instances with few detectable copies are hypothesized to form larger structures by dimerization; each WD40 sequence repeat forms the first three strands of one blade and the last strand in the next blade; the last C-terminal WD40 repeat completes the blade structure of the first WD40 repeat to create the closed ring propeller-structure; residues on the top and bottom surface of the propeller are propos

WD40域，在真核蛋白质的数量发现，涵盖了包括各种功能适配器/信号转导，mRNA前体细胞骨架组装加工和管理模式；通常包含一个从11月24日生长激素肽的N残留端和西部数据肽在其C端和40残留长，因而得名WD40；介于生长激素和WD一个保守的核心，作为一个稳定的螺旋桨式平台，可以绑定的蛋白可以稳定或可逆，形成了一个螺旋桨式与每个刀片是一个四叶片结构组成若干链反平行的β-片；与数份检测实例假设，形成了聚大结构，每个WD40重复序列形成了前三个一个刀片和绞线的最后在未来的刀片链，最后C -末端WD40重复完成了第一WD40重复叶片结构，创造螺旋桨的封闭环结构，对螺旋桨顶部和底部表面残留的建议，配合和其他蛋白质的相互作用/或小配体； 7重复副本，目前这条路。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

We have no common name for a mime of Sophron or Xenarchus and a Socratic Conversation; and we should still be without one even if the imitation in the two instances were in trimeters or elegiacs or some other kind of verse--though it is the way with people to tack on 'poet' to the name of a metre, and talk of elegiac-poets and epic-poets, thinking that they call them poets not by reason of the imitative nature of their work, but indiscriminately by reason of the metre they write in.

索夫农 、森那库斯和苏格拉底式的对话采用的模仿没有一个公共的名称；三音步诗、挽歌体或其他类型的诗的模仿也没有——人们把&诗人&这一名词和格律名称结合到一起，称之为挽歌体诗人或者史诗诗人，他们被称为诗人，似乎只是因为遵守格律写作，而非他们作品的模仿本质。

The relationship between communicative competence and grammar teaching should be that of the ends and the means.

交际能力和语法的关系应该是目标与途径的关系。