查询词典 hardware instruction retry

The text inside describes the system hardware work principle in brief first, and attach with the system hardware design frame diagram, combine development history that introduced the single a machine microprocessor, discuss this graduate design a function for applied each hardware connecting a people the technique connects with each one a mold piece and work processes, combine to describe in a specific way 8052,8279 and the SED1520 circumscribes the electric circuit connects oscular and soft, the hardware adjusts to try.

正文中首先简单描述系统硬件工作原理，且附以系统硬件设计框图，并介绍了单片机微处理器的发展史，论述了本次毕业设计所应用的各硬件接口技术和各个接口模块的功能及工作过程，并描述了8052、8279及SED1520外接电路接口的软、硬件调试。

China Hardware Products Association has formally agreed in 2006 to the General Assembly at its forty-ninth World Hardware, China and the Cologne exhibition company exhibition jointly organized by the China International Hardware, also become the world's most influential hardware industry exposition.

中国五金制品协会已经正式获得2006年第四十九届世界五金大会的承办权，而中国与德国科隆展览公司联手举办的中国国际五金展也成为世界五金行业最具有影响力的展会。

Combining the teaching practice of analytical geometry, this article puts forward the implement strategy of instruction of mathematics study: penetrate the principle of mathematics study towards the students; instruct the students how to study; help the students form the better non-intellect factor; develop the student's original cognizance level; present the instruction of mathematics study ; raise the extent of students' participation ; keep the teaching and instruction in harmony and instruct the solution of students' query.

结合立体几何教学实践，本文提出了数学学法指导的实施策略：向学生渗透数学学习方法理念：对学生学习的各环节进行学习方法指导；对学生形成良好的非智力因素进行指导；发展学生的元认知水平；数学学法指导的基本方法；提高学生的智力参与程度；教学与学法指导和谐统一；对学生质疑问难的方法进行指导。

Thus, whenever a branch instruction is encountered the disassembly continues simultaneously at both the address following the branch instruction and the address that is the target of the branch instruction.

因此，无论何时遇到一个分支指令，就同时从两个地址继续反汇编：分支指令后面的地址和分支指令的目标地址。

The idea of Autonomous Instruction Memory is to combine Top-Level Instruction Memory and Branch Target Buffer. This kind of architecture has an character of self-generating instruction address.

自主指令记忆体的设计的想法在於结合动态分支预测器和最上层的指令记忆体而拥有自行产生指令位址的特性，因而使得CPU可以不用传送指令位址给自主指令记忆体，而达到降低CPU和自主指令记忆体之间指令位址汇流排上传递资料量的目的。

This will lead the recursive traversal algorithm to follow both the paths, the instruction immediately after the conditional jump instruction and the target of the jump instruction, potentially leading to an inconsistent state.

它将引导递归遍历算法跟随这两个路径：条件跳转指令之后紧接的那条指令和跳转指令的目标，潜在地导致一个不相容的状态。

Because SBB is going to set EAX either to zero or to 0xffffffff, we can consider the following AND instruction to be similar to a conditional assignment instruction (much like the CMOV instruction discussed later).

我们先从"与"指令说起，因为根据减法的结果，SBB将eax寄存器设为全F或全0，我们可以推出逻辑"与"的结果等价与一个条件赋值语句(类似于我们后面会讨论的CMOV指令)。

Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

基于上述结论，为了尽量消除转移指令对处理器开发指令级并行性能力的影响，进一步提高处理器性能，在详尽分析目前已存在的转移处理策略的特点与局限性的基础上，首次提出了一种新的转移处理策略即基于分类的层次转移处理策略CHBHS(Classification Based Hierarchical Branch Handling Strategy)，它首先通过扩展传统的体系结构，支持多条件码、条件式执行及多分支转移技术，以使编译程序在进行代码生成时可尽量少生成条件转移指令，从而减少静态条件转移指令的数目；其次，基于不同的转移指令的行为不同这一事实，提出了对不同的转移指令采用不同的机制进行处理的思想，即对无条件转移指令和函数调用指令以及条件转移指令的目标地址，采用转移目标缓冲器来预测，对于函数返回指令，采用所提出一种的高效返回地址栈来预测其目标地址，对于大多数循环控制转移指令，采用所提出的Counter Register Stack来将其所可能带来的损失减少为0，对于其他的条件转移指令采用动态预测机制来预测其方向。

To throw the disassembly off, the garbage data may be crafted so that it matches a valid instruction, thus beating a heuristic that validates the instruction after the jump instruction.

为了使反汇编陷入窘境，无用数据可能是由手工打造以便让它匹配某个有效指令；以此挫败启发式验证跳转指令之后的指令是否有效。

The controller uses the data write buffer to reduce the data access waiting time, and employs the two ways of duo channels instruction pre-fetch buffer to decrease the fetching instruction waiting time and increase the instruction pre-fetch buffer hit rate. Meanwhile, to reduce the waiting time aroused by page miss of SDRAM, a four ways of on chip stack memory is introduced. Compared with traditional controller through experiments the novel SDRAM controller gets a high reduction up to 63% in access waiting time and 64% in page miss.

该控制器采用数据写缓存方式降低了数据在存取内存时的等待时间；并引入了两组双通道预取指令缓冲器，每组双通道都用以减少取指令时的等待时间，采用两组的结构是为了增加指令预取的命中率；同时还使用了四路组关联的片上堆栈存储器来降低SDRAM的页失效频率，从而降低了因页失效而需要等待的时钟周期。

Objective To study the effect of chitosan in the prevention of fibrous scar formation in the epidural space after laminectomy.

目的 观察选择性脊神经后根切除术椎板切除后硬膜外几种防瘢痕粘连物质的作用并探讨其机制。

On his way to the lift, he looked back to us or was it me his eyes pointing?

当他要进电梯时，他回头看我们（或者说是我，他的眼光？