查询词典 h.v.

Test results of EMP-steel frictional pairs showed that the wear rate h of EMP, press p andvelocity v are suited to equations separately: h =m .p n and h =a .v b.

试验证明EMP复合材料瓦与钢对磨时的磨损率h与压力p、速度v之间分别满足h=m.pn和h=a.vb关系式，给出了相应系数m、n、a、b的值；磨损率与钢试件表面粗糙度Ra之间满足h=A·RaB关系式，给出了A、B的有效范围值。

XRD results indicate that the major diffraction peaks of the film match those of Sb2Te3. The film growth is apparently at the ［101］/［012］ orientation and many Te peaks are observed. Hall measurement reveals that all the samples are p-type and the resistivities are low. The electric conductivity of the films approaches that of the bulk metal and the carrier concentration is of 1023 cm-3. Seebeck coefficient measurement shows that the samples have nice thermoelectrical properties and the seebeck coefficients are in the range of 7.8—62 μV/K. Among all, the samples annealed at 200 ℃ for 6 h have the highest seebeck coefficient of about 62 μV/K and the lowest resistivity.

XRD测量结果显示，薄膜的主要衍射峰与Sb2Te3标准衍射峰相同，在［101］/［012］晶向取向明显，存在较多的Te杂质峰；霍尔系数测试结果表明，薄膜为p型半导体薄膜，薄膜电阻率较低，其电导率接近于金属电导率，载流子浓度量级为1023 cm-3，具有良好的电学性能；Seebeck系数测量结果显示，薄膜具有良好的热电性能，在不同条件下制备的薄膜的Seebeck系数在7.8—62 μV/K范围；在所制备的薄膜中，退火时间为6 h、退火温度为200 ℃的薄膜其Seebeck系数达到最大，约为62 μV/K，且电阻率最小。

Using intact tonoplast proteins, the effect of Ca〓-dependent phosphorylation on the activity of V type H〓-ATPase has been observed.

在完整的液泡膜囊泡水平观察了钙依赖的磷酸化作用对V型H〓-ATPase的活性调节，发现已磷酸化的V型H〓-ATPase的ATP水解活性和质子转运活性均有了较大的提高。

In general, V-H+_ATPase activity is increased in salt-tolerant plant species, which presumably results from the increased genetic expression and synthesis of tonoplast H+_ATPase subunits under saline conditions.

盐胁迫提高抗盐植物液泡膜H+_ATPase活性，主要是通过增加V型H+_ATPase主要功能亚基的基因表达以及蛋白质合成。

In the studies on transferring and identifying alien chro-mosomes into wheat,the combined use of mitotic and meioticchromosome N-banding is also successfully practiced in deter-mination of T.durum-H.villosa amphipoid,five wheatalien disomic additions with H.villosa chromosomes,〓〓,alien sulstitution line with chromosome 〓 andsome translocation lines.

在外源染色体导入、鉴定研究中，利用根尖有丝分裂中期染色体和花粉母细胞减数分裂中期Ⅰ染色体的N-分带，快速、准确地鉴定了硬粒小麦一簇毛麦双二倍体、普通小麦一簇毛麦异耐加系V〓、V〓、V〓、V〓和V〓，普通小麦一簇毛麦异代换系V〓以及一些具有易位的杂种后代。

Methods: Electrets Teflon PTFE,±300 V,±1 000 V were used to treat 3T3 cells for 24, 48 and 72 h. Then the influences of electrets on cell cycle and surface charge of 3T3 cells were studied by flow cytometry and electrophoresis, respectively.

选用±300 V和±1 000 V驻极体分别作用成纤维细胞24、48和72 h，用流式细胞术和细胞电泳技术测定成纤维细胞的生长周期和细胞表面电荷。

Methods: After 48 h action of -300 V and -500 V electrets in 3T3 cells, CaCl2, A23187, EDTA were added in proper order to 3T3 cells. The levels of intracellular Ca2+ and the cell number of apoptosis were detected with flow cytometry.

选用-300 V和-500 V 驻极体作用3T3细胞48 h，即时依次加入CaCl2、A23187、EDTA，通过流式细胞术检测细胞内Ca2+浓度的变化和3T3细胞的凋亡量。

Results: Compared with control group, apoptosis cells increased from 0.5%to 10%(some even to 15%) after 24,48 and 72 h action of -300,-500 and -1 000 V electrets. After action of -500 V PTFE electrets for 48-72 h, fibroblast cells showed characteristic morphological features of apoptosis. These features included chromatin aggregation, nuclear and cytoplasmic condensation and partition of cytoplasm and nucleus into membrane bound-vesicles.

结果：-300、-500和-1 000 V驻极体作用成纤维细胞24、48和72 h以后，与对照组相比，成纤维细胞的凋亡量从0.5％增至10％（部分可达15％）；驻极体作用成纤维细胞48～72 h，出现细胞凋亡特有的形态学特征，即：细胞异染色质边集，细胞裂解，可见凋亡小体。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Plunder melds and run with this jewel!

掠夺melds和运行与此宝石！

My dream is to be a crazy growing tree and extend at the edge between the city and the forest.

此刻，也许正是在通往天国的路上，我体验着这白色的晕旋。