查询词典 gate voltage

A new folded differential pair topology based on quasi-floating gate technique is presented, and an ultra-low voltage op amp based on this structure is designed.

提出了一种基于准浮栅技术的折叠差分结构，基于此结构设计，实现了超低压运算放大器。

And the influence of bias voltage, power and width of the pump pulse on the EAM gate is analyzed respectively.

同时， 进行了开关门特性与偏置电压大小和抽运脉冲功率之间关系的实验研究。

The transport and current-voltage properties of submicron GaAs MESFET device are calculated firstly based on the nonparabolic effective mass energy band model and Monte Carlo method which includes all major scattering mechanisms. The electron drift velocity, electric field and the non-homogeneity of mobility distribution in device are obtained. The influences of different gate lengths to electron drift velocity and drain current are analyzed.

根据对以GaAs、GaP和InP为主的Ⅲ-V族化合物半导体材料的能带结构和散射机制的分析，采用蒙特卡罗模拟方法，研究了亚微米尺寸的OaAs MESFET器件的电子密度分布、电场强度、漂移速度和迁移率分布等输运性质，以及栅长对器件性质的影响和电流电压特性。

Issues added: GTO below the opening of the process and shutdown process: Located GTO anode forward voltage electric pressure, when the increase in positive gate trigger current IG, through N1P2N2 transistors amplification makes its collector current IC2 and emitter current IK increase.

问题补充：下面分析GTO的开通过程和关断过程：设GTO阳极电压力正向电压，当在门极加正向触发电流IG后，通过N1P2N2晶体管的放大作用使得其集电极电流IC2和发射极电流IK增加。

As a result, a breakdown voltage of an oxide film, which occurs in the gate oxide film, can be prevented.

结果，可以防止发生在栅极氧化膜中的氧化膜的击穿电压。

Key words: communication technology; jitter generator; equivalent noise voltage model; jitter; field programmable gate arrayFPGA

关键 词：通信技术；抖动发生器；等效噪声电压模型；抖动；现场可编程门阵列

Simulation results show that the doping profile and width of P base region are important to the on-state voltage drop of Gate Controlled Thyristor.

模拟结果表明，P基区的掺杂浓度和宽度对门极换流晶闸管通态压降有着重要的影响。

The reason of appearing peak voltage in IGBT(insulated gate bipolar transistor)absorber is discussed.

探讨了IGBT功率电路尖峰电压产生的原因，并针对第三代IGBT，给出了适应不同功率的吸收电路。

7 To 3.3 V operating supply voltage 44.1 kHz sampling frequency 16.9344 MHz (384fs) system clock Built-in crystal oscillator circuit 16-bit, MSB rst, rear-packed serial data input format ( 64 fs bit clock) 8-times oversampling digital lter · 32 dB stopband attenuation ·+0.05 to -0.05 dB passband ripple Deemphasis lter operation · 36 dB stopband attenuation ·-0.09 to +0.23 dB deviation from ideal deem- phasis lter characteristics Attenuator · 7-bit attenuator (128 steps) set by microcontrol- ler Soft mute function set by parallel setting ·(approximately 1024/fs total muting time) Mono setting · Left or right channel mono selectable by micro- controller Built-in innity-zero detection circuit , two-channel D/A converter · 3rd-order noise shaper · 32fs oversampling Built-in 3rd-order post-converter low-pass lters 24-pin VSOP package Molybdenum-gate CMOS process

2.7至3.3 V工作电源电压为44.1千赫的采样频率16.9344兆赫（384fs）系统时钟内置晶体振荡器电路的16位，MSB在前，后包装的串行数据输入格式（64飞秒位时钟）8倍超采样数字滤波器·32分贝的阻带衰减·+0.05至-0.05分贝通带纹波去加重滤波器的运作·36 dB抑制频宽衰减·-0.09到0.23 dB的偏差认为不理想，症状困扰评估滤波特性衰减器·7位衰减器（128级）集由单片机在-莱尔软静音功能的平行设置·（共约1024/fs静音时间）单声道设置·左或右声道单声道微控制器可选的内置的无限零检测电路Δ，两通道的D / A转换器·第三阶噪声整形·32fs过采样内置三阶后转换器的低通滤波器24引脚VSOP封装钼栅CMOS工艺

An analog control, in accordance with corresponding changes in the load modulation transistor gate of the base or bias, to achieve the output transistor switching power supply or transistor turn-on time of change in this way can the power supply output voltage in the workplace Conditions of constant change.

一种模拟控制方式，根据相应载荷的变化来调制晶体管栅极或基极的偏置，来实现开关稳压电源输出晶体管或晶体管导通时间的改变，这种方式能使电源的输出电压在工作条件变化时保持恒定。

Do you know, i need you to come back

你知道吗，我需要你回来

Yang yinshu、Wang xiangsheng、Li decang,The first discovery of haemaphysalis conicinna.

1〕 杨银书，王祥生，李德昌。安徽省首次发现嗜群血蜱。