查询词典 emulation mode

Of course all this may be further developed by omitting the emulation of the indicator mode of buffers' operation.

当然，这一切都可能会得到进一步的发展省略仿真的指标模式的缓冲器'的运作。

We may suppose that it is somehow connected with using emulation of the indicator mode of buffers operation and returning values by indicator functions into buffers by reference.

我们可以假设它是某种与用仿真的指标模式的缓冲器运行和返回值由指标的功能到缓冲器参考。

This text sets out from the actual,providing a kind of emulation project to the tunnel mode,providing some technique investigate for the coming network transfer period adoption tunnel mode.

本文从实际情况出发，对隧道模式提供一种可行的模拟方案，为即将到来的网络过渡[1]时期采用隧道模式提供一定的技术探索。

The flexible body concept is introduced to constitute the virtual prototyping continuum model of the longitudinal vibration and the transverse vibration of the belt conveyor in the thesis, and the two virtual prototyping models are analyzed in an emulation mode.

本文将柔性体概念引入带式输送机纵向振动连续模型虚拟样机和带式输送机横向振动虚拟样机的建立中，并对这两种虚拟样机进行了振动仿真分析。

In order to verify safety,efficiency and high quality of high-speed cutting machining,I d like to analyze the whole manufacturing process;from drawing up the steps of mould machining;taking rough machining,semi-finish machining and finish machining into account,and designing a reasonable machining scheme through emulation mode to meet the demand of high-speed cutting machining.

为了验证高速切削技术的安全、高效和高质量特性，从一个高速铣削加工任务开始，分析了高速加工模具工艺制订步骤，把粗加工、半精加工和精加工作为一个整体考虑，设计出合理的加工方案，通过仿真达到高速切削技术的要求，并通过实际加工，得出与传统工艺电火花线切割加工对比后的试验数据，论证了高速切削工艺的高效和经济性。

Z80 and SNA snapshots. Joystick emulation mode Sound Landscape only to SPV joypad Automatic saving of states on exit and reload.

Z80和SNA的快照。操纵杆声景观仿真模式只专门机构joypad自动节能的国家退出并重新载入。

The result indicates that it is not excellent beyond the current research method except obtaining the more dynamic parameters, although the virtual prototyping continuum model of the longitudinal vibration and the transverse vibration of the belt conveyor is analyzed in an emulation mode.

分析结果显示，虽然建立带式输送机纵向振动连续模型和横向振动连续模型虚拟样机进行仿真分析，可以比现有方法得到更多的动态参数，但是，并不能超越现用方法的研究范围。

in basic of a hypothesis, a emulation calculate mode about the steady available of the weapon equipment was formed. emulation calculate process was compiled by using matlab6.5 engineering calculate software. a front-alternating interface was made in virtue of visual basic6.0 program language, and the data transfers was realized by using dde of windows operating system.

在一定假设的基础上，建立了武器装备稳态可用度仿真计算模型，利用matlab6.5工程计算软件编制了仿真计算程序，借助visual basic6.0编程语言制作了前端交互界面，并通过windows操作系统特有的动态数据交换机制实现了数据的传输。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Singer Leona Lewis and former Led Zeppelin guitarist Jimmy Page emerged as the bus transformed into a grass-covered carnival float, and the pair combined for a rendition of "Whole Lotta Love".

歌手leona刘易斯和前率领的飞艇的吉他手吉米页出现巴士转化为基层所涵盖的嘉年华花车，和一双合并为一移交&整个lotta爱&。

This is Kate, and that's Erin.

这是凯特，那个是爱朗。