查询词典 dual

In order to reduce the conflict of L1P in CMT,we propose the policy of logic partition L1P Cache by n power of 2 and the competing loop lock.Now the fairness researchs always need single thread sample phase,we propose a novel fairness policy:FROCM,it doesn\'t need single thread sample phase.We propose ring cooperant L1 data Cache,which can reduce both the complexity of the design and the load of L2 Cache.We also propose a method to exchange threads dynamicly based on fast-shared data pool,it can detect the data consanguinity of two threads in real time and exchange them into one core rapidly.At last,we design and implement a dual-core and dual-thread VLIW prototype YHFT DSP/DS based on the above studies.In order to enhance the bandwidth of data path and reduce the delay of critical path delay of CMT processor,we design a 10R/6W register file full customly.

为了减小多线程运行时指令Cache的冲突，本文提出了二幂等分指令Cache策略和循环锁竞争机制；现有对CMT处理器公平性的研究常常需要中断其它线程进行单线程采样，针对这个问题本文提出了多线程公平性策略FROCM；本文提出了环形协同数据Cache结构，以解决CMT处理器中共享存储体负载重，冲突大的问题；本文还提出了基于快速共享数据缓冲池的线程动态交换技术；最后本文实现了一个双核同时多线程芯片原型YHFT DSP/DS。

Base on the analysis of the grating linear displacement measurement theory,t he measure errors especially the subdivision error of the grating scale,this paper focuses on the theory of switch and merge of dual grating scales'signals,builds the design criteria of high speed high precision displacement measurement by using dual grating sales,designs the switch picking reference with high precision and fast switch and merge method,analyses the errors brought in by switch and merge of the duals grating scales.

针对光栅尺的电子细分信号具有细分误差的特性，本文提出了对莫尔条纹信号不细分的方法以提高双光栅尺信号切换合成值的精度。经过对双光栅计数切换基准、切换与合成特征和规律的探讨，本文设计了实现双光栅尺双重测量、计数值切换合成法的硬件电路，主要通过可编程芯片FPGA，设计了双光栅尺信号处理的各电路模块，如双光栅尺信号四倍频辨向模块、速度判断模块、切换模块、计数值合成处理模块。

A duplexer separates an RF signal received from the built-in dual band antenna from an RF signal to be transmitted to the built-in dual band antenna.

双工器分离从内置双频带天线接收的无线电频率信号和要发送到内置双频带天线的RF信号。

Beginning with the theory of the DC timing system,this article has built up the maths model of the reversible DC-PWM timing system with a dual-converter and dual-closed-loop,Given the details of the system design, software and hardware design, circuit structure and control algorithms using the PI process control proce- dures.

从直流调速系统原理出发，逐步建立了双闭环直流PWM调速系统的数学模型，给出了该系统的详细设计思路、软硬件设计、电路结构和采用PI控制算法的控制程序流程。

The aim of this text is about how to serve the students better in their special field of study, train their interests in maths studying and how to fully reflect the quintessence of dual system.Key words : Dual system educational system; the thought based on ability; teach students according to their level; interest

本文拟就将从&双元制&模式下数学怎么更好地为学生学习专业课程服务，培养学生学习数学的兴趣，在数学学习中怎样秉承以能力为本位的&双元制&教育制度的精髓等五个方面进行初浅的探讨。

I Division is specialized in producing dual-metal temperature control for Hong Kong enterprises,(specializing in the production of iron, electronic oven, heater machine, hairdryer with temperature control) plot has produced more than 10 years of experience with temperature control, product selection World-class imported raw materials, technical skills, improve the system-management system, the company's products exported to Europe and the United States and Southeast Asian markets, in production for a long time and several major brand-name manufacturers the world maintained a good supply of products from long-term cooperation with the manufacturers have (Wal-Mart China Co., Ltd., Shenzhen practical Electric Co., Ltd., and other well-known large enterprises) with an annual output of dual-metal temperature control for more than 20 million.

我司是专业生产双金属片温控器的港资企业，(专业生产电熨斗、电烤箱、暖风机、电吹风用温控器)积有十余年生产温控器的丰富经验，产品精选世界一流的进口原材料，技术精湛，管理体系健制完善，本公司产品远销欧美和东南亚市场，在生产上长期与世界几大名牌厂家保持著良好的产品供应往来，长期与之合作的厂家有（沃尔玛中国有限公司，深圳实用电器有限公司、等知名大企业）年产双金属片温控器2000万件以上。

An analysis of the phase noise and reference spur of the dual-loop PLL is emphasized. A novel multiple-pass ring VCO is designed for the dual-loop application.

文中对这种双环路锁相环的相位噪声和参考时钟杂散特性进行了着重分析，结果表明这种结构能够提高相位噪声特性。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Even among the traitors and pro-Japanese elements there are people with a dual character, towards whom we should likewise employ a revolutionary dual policy.

即在汉奸亲日派中间也有两面分子，我们也应以革命的两面政策对待之。

This one mode pays close attention to network credence foundation of the businessman very much.

这一模式非常关注商人的网络信用基础。

Cell morphology of bacterial ghost of Pasteurella multocida was observed by scanning electron microscopy and inactivation ratio was estimated by CFU analysi.

扫描电镜观察多杀性巴氏杆菌细菌幽灵和菌落形成单位评价遗传灭活率。