查询词典 dual basis

To further enhance the autoleveling technology of drawing frame, a new type of dual open-loop control system was issued based on the analysis of the quality of the current autoleveling control system of drawing frame. This paper presented a mathematical model of the new control system, analyzed its mathematical theory, and elucidated the theoretical basis of dual open-loop autoleveling control system.

为进一步提高并条机自调匀整技术，在分析纺织并条机自调匀整控制系统优劣的基础上，提出一种新的双开环控制系统，给出了新型控制系统的数学模型，详细分析了其数学原理，阐述了双开环自调匀整控制系统的理论基础。

The contents involve the recursion algorithms, the dual functional of SBGB basis and the transformation formula between SBGB basis and Bernstein basis.

给出它们的递归算法，SBGB基函数的对偶泛函，并由此得到SBGB基函数与Bernstein基函数转换公式。

By making a thorough study of WSGB curves, the author acquires two main results, i.e., the transformation formula from Bernstein basis to WSGB basis and the construction of the dual functionals for WSGB basis functions.

利用特殊多项式的分解与展开，推导出从Bernstein基函数到WSGB基函数的转换公式。 2。构造出WSGB基函数的对偶泛函，并应用WSGB基函数的对偶泛函，得到另一种方法实现WSGB曲线与Bézier曲线的互相转化。

Such pure software used method of dual module hot spare system that can improve system reliability on the basis of reduce the use of hardware dual module hot spare mechanism of the complexity and development costs, also be able to shorten the development cycle to achieve the purpose.

这种采用纯软件方法实现的双机热备系统，可以在提高系统可靠性的基础上，降低采用硬件开发双机热备机制的复杂性和开发成本，同时也能够达到缩短开发周期的目的。

A simultaneous dual-wavelength continuous wave, quasi-cw or linearly polarized wave diode-end-pumped Nd:YAG laser operating at 1319nm and 1338nm is demonstrated. To the best of our knowledge, our experimental results achieve the highest level in the domestic domain. The simultaneous dual-wavelength laser provides an experimental basis for generating highly coherent THz wave radiation of 3.23THz by nonlinear optical difference frequency method.2. A diode-end-pumped Nd:YAG crystal, type-I critical phase matching LBO crystal intra-cavity frequency doubled, simultaneous multi-wavelength red laser at 659.5nm, 664nm and 669nm is firstly realized.

本论文主要围绕用于差频产生THz辐射源的多波长激光器及THz光子晶体的带隙特性分析而展开，论文的主要内容包括：一、从LD端面泵浦固体激光器的激光阈值公式出发，理论计算了腔镜对于两个波长的透过率关系，实现了LD端面泵浦Nd：YAG 1319nm/1338nm双波长激光连续、准连续及线偏振稳定输出。

Moreover, we give some dual properties of these problems, and on this basis, we present a dual algorithm for solving the nonconvex conic model trust-region subproblem.

论文分析了这些问题的对偶性质，在此基础上，通过对偶提出了求解锥模型信赖域子问题的算法，同时证明了算法的全局收敛性以及局部Q-超线性收敛性，并给出了一些数值算例以说明算法的有效性。

On the basis of forenamed, Chapter 4 put forward that cooperation system was a new way to push the dual economic structure"s conversion. This chapter was consisted of there parts, first, it proved that cooperation system was the inevitable choice of peasant; second, it introduced four steps to advance the dual economic structure"s conversion of our country; at last, it introduced other reformations which coincide with cooperationsystem.

第四章在以上分析的基础上，提出合作制是推进我国二元经济结构转化的新思路，包括三个方面的内容，一是论述了合作制是农民的必然选择，介绍了合作制的定义，分析了农民选择合作制的原因，并说明合作制可以解决我国传统解决办法的不足；二是介绍了以合作制推进我国二元经济结构转化的四部曲，这四部曲是一般过程，每个地区都可以根据本地的条件有所取舍；三是介绍了以合作制推进我国二元经济结构转化需要的配套改革措施，首先，要统筹城乡的制度建设，其次，一定要把政府的扶持和农民的积极自救相结合。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

On the basis of analyzing the output signal of a two wavelength beat-wave absolute distance interferometer, this paper proceeds from the realities of the aiming method of the beat-wave interferometer, conducts an analytical investigations on the dependence of the aiming accuracy of the beat-wave interferometer on laser dual-line output power equilibrium, propose two new concepts-a basic aim blind area and a blind area expansion, and establishes an analytical expression between the blind area expansion and the relative power difference of laser dual lines.

本文从拍波干涉仪对准方法的实际出发，在分析双谱线拍波干涉仪输出信号的基础上，研究了双谱线功率不一致与拍波干涉仪对准精度的关系，提出了基本对准盲区和盲区扩大量的新概念，建立了描述盲区扩大量与双谱线相对功率差之间关系的解析表达式。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。