查询词典 digital signal

This paper systematically researched this sort of nonuniformly sampled signals'digital spectrum structure, signal-to-noise ratio , the response of D/A converter with nonuniformly sampled signals, the algorithm for estimating timing offsets, the relationship between the discrete time expression of the total energy and the continuous time expression, the estimation of the average power, the algorithm of recovery and application in designing and analyzing the digital waveform synthesizer.

本文全面系统地研究了这类周期性非均匀采样信号的数字谱结构，信噪比表达式，数模转换器对非均匀采样信号输入的响应，误差校正算法，时域与频域的能量对应关系，对功率测量的影响，内插恢复算法，以及在设计和分析数字波形合成器中的应用。

The digital frequency source this paper researched uses high integrated DDS chip AD9851 as frequency sources and signal mirac processors AT89C51 as system control center, it can output 10Hz-20MHz signal with high-precision and high stability frequency.

毕业论文字数：15850 页数：36）摘要：随着现代电子技术的发展，高精度数字频率源在通讯、雷达、宇航、电视广播、遥控遥测、电子测量等领域得到了广泛的应用。

Really, white doctor is at the outset in digital TV industry arduous and cultivated when, he cannot think of probably, the United States already had the family that is as high as 70% above to turn into digital TV platform entirely nowadays, now summerly Beijing Olympic Games more came true first the number of whole journey is high-definition the direct seeding of signal.

确实，白博士当初在数字电视产业中辛勤耕耘时，他或许并没有想到，如今美国已有高达70%以上的家庭全部转入了数字电视平台，而今夏北京奥运会更实现了首次全程的数字高清信号的直播。

The system makes use of cooperation of artificial circuit and digital circuit to produce tristate neural stimulating signal and achieve signal collec-tion and LCD screen real time display of stimulating .

利用模拟电路和数字电路配合产生了三态的神经刺激信号。基于DSP控制成功的实现了信号采集和刺激的液晶屏实时显示。

In the telecom devices and digital networks, it can guarantee the digital or analogy signal which is transformed has low attenuation and unconspicuous distortion. All of these requests determine the important status of transmission line transformers in modern telecommunication.

包括在电信设备和数字网络中，要求使传输的模拟或数字信号有低的衰减，以及无明显的失真，这些都决定了传输线变压器在现代通信中的重要地位。

In this thesis, an all-digital phase-locked loop with large multiplication factor is presented. This circuit can be applied to the video system as a clock generator. It receives the horizontal synchronous signal from the graphics card and then generates a high frequency pixel clock according to the monitor resolution setting to acquire the video signal data. The stability of this sampling clock affects the display image quality directly. If the pixel clock is not stable, the display image will be glittering or jittering.

在本论文中，我们提出一个高频率倍数的全数位式锁相回路，此电路可应用於视讯系统中的时脉产生器，其主要功能是接收显示卡发出的水平同步讯号，并依据使用者设定的萤幕解析度，产生高频像素时脉来撷取视讯讯号资料，取样点的稳定度直接影响到显示画面的品质，若是像素时脉不稳定，则显示画面会闪烁或抖动。

A mode buffer and command block (560) uses the mode signal to control the creation of initial and final digital words created by a data buffer and control block (550) from the digital data sequence.

一个模式缓冲和命令块（560）使用模式信号，控制由一个数据缓冲和控制块（550）从数字数据序列所生成的初始和最后数字字的生成。

The A to D converter converts the analog signal to a digital file or signal.

A 转换器传输到D转换器（模拟转换器转换到数字转换器）将模拟信号转换到数字文件或信号。

Location among them draw function to utilize digital phase locking ring produce the synchronous signal in the location to draw from code array in step, and regard this signal as the clock of the part of the decoder.

其中的位同步提取功能是利用超前滞后型数字锁相环从编码序列中提取出位同步信号，并把该信号作为译码部分的时钟。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

But we don't care about Battlegrounds.

但我们并不在乎沙场中的显露。

Ah! don't mention it, the butcher's shop is a horror.

啊！不用提了。提到肉，真是糟透了。