查询词典 digital clock

A7800 Features: 10 Mb s Manchester encoding decoding with receive clock recovery Patented digital phase locked loop decoder re- quires no precision external components Decodes Manchester data with up to g18 ns of jitter Loopback capability for diagnostics Externally selectable half or full step modes of opera- tion at transmit output Squelch circuits at the receive and collision inputs re- ject noise High voltage protection at transceiver interface (16V) TTL MOS compatible controller interface Connects directly to the transceiver cable A7800 Maximum Ratings: A7800 Pinout:· NPT IGBT technology · low saturation voltage · low switching losses · switching frequency up to 30 kHz · square RBSOA, no latch up · high short circuit capability · positive temperature coefficient for easy parallelling · MOS input, voltage controlled · ultra fast free wheeling diodes · solderable pins for PCB mounting · package with copper base plate

A7800特点： 10兆s曼彻斯特编码与接收时钟恢复专利解码数字锁相环解码器重新奎雷斯没有精确数据的外部元件曼彻斯特解码高达全部G18抖动纳秒环回功能用于诊断外部可选的一半或整步模式的歌剧和灰在传输和接收碰撞投入重新ject高噪音在收发器接口（16V的）马鞍山的TTL兼容控制器接口电压保护输出静噪电路直接连接到收发器的电缆 A7800最大额定值： A7800引脚说明：·不扩散核武器条约IGBT技术·低饱和电压·低开关损耗·开关频率可达30千赫·平方米RBSOA，没有锁定了高短路能力··正温度，便于parallelling·马鞍山消耗系数，电压控制·超高速免费·印刷电路板焊接的引脚安装·铜底板包续流二极管

And optimization techniques have been presented, which cover the key blocks of pipeline ADC, such as MDACs, Sub-ADCs, clock generator, digital correction circuits etc. This research focuses on minimizing power dissipation in high speed piplined ADCs.

接着从分析流水线模数转换器系统误差来源以及流水线各级精度要求入手，着重对系统结构、MDAC、Sub-ADC、时钟发生器、数字纠错逻辑等五大模块提出优化方案。

Due to walking error of digital clock, we design time calibration circuit in the system.

针对数字钟会产生走时误差的现象，在电路中就设计有有校准时间功能的电路。

Driven by decoding output circuit, it can display showing clear and intuitive figures. Due to walking error of digital clock, we design time calibrat in the system.

在译码显示电路输出的驱动下，显示出清晰、直观的数字符号。

And by comparing the actualclock, find out the source of the error and determined the methodof adjusting error, reduce errors as much as possibly, so thissystem can achieve a practical digital clock with error within thepermissible range.

并且通过对比实际的时钟，查找出了误差的来源，确定了调整误差的方法，尽可能的减少误差，使得系统可以达到实际数字钟的允许误差范围内。

Using SiGe technology and a fully differential archi- tecture, the device offers superior digital signal characteristics and very low clock skew error.

利用硅锗技术和全差分阿尔基-丁桃源，该器件提供卓越的数字信号的特点和非常低的时钟偏移误差。

It's only been on the market for a few weeks. On top of what the Dinger has, it's got a digital clock and calculator.

它上市才几个礼拜，除了Dinger有的功能之外，它还拥有数字时钟和计算器。

Location among them draw function to utilize digital phase locking ring produce the synchronous signal in the location to draw from code array in step, and regard this signal as the clock of the part of the decoder.

其中的位同步提取功能是利用超前滞后型数字锁相环从编码序列中提取出位同步信号，并把该信号作为译码部分的时钟。

For the study MCU is a threshold in terms of this program, master of the digital clock program is basically 51 to control 80% of SCM.

对于学习单片机而言这个程序是一道门槛，掌握了数字钟程序，基本上51单片机就掌握了80%。

A durable mineral window shields the black dial face, which features luminous hour indexes, matching watch hands, and a digital display below the six o'clock position.

一个持久的矿产窗口屏蔽了黑面表盘，其特点发光小时指标，匹配手表手，以及一个数字显示下方6点位置。

Nowadays, most of research are to build a transmutative Petri Nets through adding controlling place sets, controlling arc sets and controlling policy to the basic Petri Nets, while the Controlled Petri Nets could be used to argue many controlling theory problems conveniently and to induce many logically and physically supervisory and solve the Event Feedback Controlling Problems and State Feedback Controlling Problem in DEDS supervisory theory.

目前大多数的研究表现为在变形后的受控Petri网基础上，利用各种方法求得各种逻辑型、结构型控制器，解决DEDS监控理论中的事件反馈控制问题与状态反馈控制问题。

On one hand, there are discussions with the works council and union about extension of short time working up to the end of September.

一方面，有讨论，工程理事会和联盟关于延长工作时间短至9月底。