查询词典 digital clock

The method comprises the steps of: constructing a testing system which inputs digital codes and outputs simulated values of the analog-digital converter; obtaining a comparison table which is output through inputting responded simulated values of different digital codes from 0 to 2N-1 of the analog-digital converter; calculating to obtain an integration non-linear error comparison table corresponding to different digital code input of the analog-digital converter; compensating integration non-linear errors of the analog-digital converter through a hardware compensating method of adding a subtracter; and obtaining accurate analog-digital converter output.

搭建数模转换器的数字码输入-模拟值输出的测试系统；获得数模转换器从0到2 N -1的不同数字码输入响应的模拟值输出的对照表；计算得到数模转换器相应于不同数字码输入的积分非线性误差的对照表；通过加入减法器的硬件补偿方法，补偿数模转换器的积分非线性误差，获得准确的数模转换器输出。

One focus has steel wall clock, aluminum shell wall clock, alarm clock, iron, aluminum extrusion and other metal bell, but also the production of plastic clock, wood clock, leather clock.

其中重点有铁壳挂钟、铝壳挂钟、铁闹钟、铝挤压等金属钟，也有生产塑胶钟、木头钟、皮钟。

along with the development of digital technology,digital filters are widely used in many fields,this paper introduces how to design a iir digital notch filters in matlab environment.the design of digital notch filters can be achieved through three steps:firstly,the design of analog lowpass filter; secondly,it is analog lowpass to analog band stop filter conversion;at last,using the bilinear transformation make the analog notch filters change into digital notch filters.the paper also introduces how to design the transfer function of the digital notch filters using all the zeros and farthest points at the same time,it also introduces the program of the digital notch filters under butterworth analog lowpass prototype.

摘 要：随着数字技术的发展，数字滤波器在许多领域得到广泛的应用。研究一种在matlab语言环境下设计iir数字陷波滤波器的方法，在数字陷波滤波器设计过程中，先进行模拟低通滤波器的设计，然后进行模拟低通/模拟带阻滤波器转换，最后采用双线性变化法将模拟陷波滤波器转化成数字陷波滤波器。提出一种用所有零点和极点来表达数字陷波器传递函数的方法，同时给出以巴特沃斯模拟低通为原型设计数字陷波滤波器的程序。关键词：无限冲激响应；巴特沃斯滤波器；数字陷波滤波器；matlab；双线性变换

Digital clock is a kind of modern calculagraph which is composed of digital integrated circuit and can show decimal digital. Compared with mechanical clock, it is exact and can be see frankly. It is very popular in some public places, such as station, airport.Keywords: Multisim2001; Circuit Simulation; Digital Circuit; Answer Bell

数字钟是用数字集成电路构成的、用数码显示的一种现代计时器，与机械表比，它走时准、显示直观、无机械传动装置等特点，广泛应用于车站、码头、机场等公共场所。

In this thesis, an all-digital phase-locked loop with large multiplication factor is presented. This circuit can be applied to the video system as a clock generator. It receives the horizontal synchronous signal from the graphics card and then generates a high frequency pixel clock according to the monitor resolution setting to acquire the video signal data. The stability of this sampling clock affects the display image quality directly. If the pixel clock is not stable, the display image will be glittering or jittering.

在本论文中，我们提出一个高频率倍数的全数位式锁相回路，此电路可应用於视讯系统中的时脉产生器，其主要功能是接收显示卡发出的水平同步讯号，并依据使用者设定的萤幕解析度，产生高频像素时脉来撷取视讯讯号资料，取样点的稳定度直接影响到显示画面的品质，若是像素时脉不稳定，则显示画面会闪烁或抖动。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

The main content of this thesis includes six parts. First of all, it is a comprehensive systematic introduction about RSA algorithm including the present application situation and principle of RSA algorithm----producing big prime numbers and secret keys, the encryption arithmetic for information and the decryption for secret information, which establish the theory foundation for achieving concrete; secondly, it introduces some basic conception of RSA digital signature and theory of digital signature realizing process; thirdly, it introduces the basic principle of MD5 algorithm; fourthly, it states design and realization of RSA digital signature in detail. The main modules includes producing RSA secret keys, implementation of RSA encryption algorithm and decryption algorithm, producing message digest and realizing digital signature and verification by RSA; the fifth, it carries on testing entirely, analyzing and improving for this system;The sixth, it analyses the security of RSA digital signature and points out the development direction of RSA digital signature.

本文主要研究的内容包括：第一，对RSA算法进行了全面系统的介绍，包括RSA算法的应用现状和原理—大素数的产生、密钥对的产生、对明文的加密运算和密文的解密运算，为具体实现打下了理论基础；第二，介绍了RSA数字签名的一些基本概念和数字签名的理论实现过程；第三，对MD5算法基本原理的介绍；第四，详述了RSA数字签名的设计与实现，主要实现的模块包括RSA密钥的产生，RSA加密算法和解密算法的实现，消息摘要MD的生成以及利用RSA算法实现数字签名和签名的验证；第五，对该系统进行了整体的测试和分析改进；第六，分析了RSA数字签名的安全性，指出了RSA数字签名的发展方向。

In this paper, the concept of network security and security structures of OSI and Internet is introduced, and various threats confronting the computer network are also discussed. Several kinds of network information security technologies, including firewall technology, virtual private network, intrusion detection system, data encryption technology, identity authentication and security protocol etc. are also examined. The security of internal network is the biggest problem in the construction of each network. The solution to this problem lies in setting up a firewall. The theory of a firewall and the approach to its actualization is studied. Intrusion detection system, an important part of the computer network security system, has gained extensive attention. IDS monitors the computer and network traffic for intrusion and suspicious activities. It not only detects the intrusion from the extranet hacker, but also the intranet users. The emergence of virtual private network paves the way for realizing secure connection of LAN quickly and at a relatively low cost. The concept, function, key techniques, including the tunnel technology, and the ways to realize VPN are expounded in this paper. Also introduced is the data encrypt network technology, which is called the soul of computer network security, such as digital digest, digital signature, digital certificate, digital encrypt arithmetic and so on. At the same time, the principle and the process of implementing network security by digital certificate and digital signature, the basic principle and characters of security protocols, and finally, three of the security protocols, concerning the security problems in network, IPsec, SLL and SET are analyzed in detail Computer network system should be a system of dynamic defence, both dynamic and static, passive as well as active, and even offensive, combined with management and technology.

本文系统地介绍了网络安全的概念、OSI及Internet的安全体系结构，并讨论了计算机网络面临的各种安全威胁；内部网络的安全问题是每个建网单位面临的最大问题，可以认为防火墙技术是解决网络安全的一个主要手段，本文研究了防火墙的原理及其实现手段；作为一种主动的防御措施，入侵检测系统作为网络系统安全的重要组成部分，得到了广泛的重视，TDS对计算机和网络资源上的恶意使用行为进行识别和响应，不仅检测来自外部的入侵行为，也监督内部用户的未授权活动；虚拟专用网技术的出现，为实现网络间的连接提供了快速安全但又相对便宜的手段，本文较深入的探讨了实现VPN的隧道技术，并对VPN的概念、功能、实现途径、基本构成、关键技术及发展前景等问题进行了全面论述；数据加密技术是网络安全核心技术之一，本文从数据加密算法、数字摘要、数字签名及数字证书等几方面简要介绍了数据加密技术，并分析用数字证书和数字签名实现网络安全的原理和过程；对安全协议的基本原理、主要特点进行了较为深入的研究，并就网络的安全性问题剖析了三种安全协议：IPsec协议、SLL协议和SET协议。

In this dissertation, digital lock-in detection techniques under integer period sampling and non-integer period sampling are separately investigated (1) Under integer period sampling, digital signal sequence is acquired through sampling the measured signal, but digital reference sequence is acquired through mathematical operation, then digital lock-in detection can be realized by calculating crosscorrelation function of digital signal sequence and digital reference sequence Harmonic measure is also analyzed, and a method of measuring harmonic of a periodic signal under aliasing is put forward.

本文对使用采样ADC把模拟信号转换为数字信号并通过计算数字信号的相关函数来实现锁定检测的技术进行了研究，在此基础上设计了一个多功能的数字LIA并在一些科学实验中进行了应用。本文对整周期采样和非整周期采样时的数字锁定检测技术分别进行了研究。(1)在整周期采样时，对被测信号进行采样得到信号序列，而参考序列由数学运算得到，通过计算信号序列和参考序列的互相关函数就可实现锁定检测。

Just so you know where we're going...

只要让你知道我们的目标。。。

One of his friends acted as the gobetween in his business.

在这件事中，他的一个朋友充当了中间人。