查询词典 digital clock

This is an interesting wall clock, take sardine can as external appearance to design, the sardine of inside even can also swing, right, that is the clock of wall clock .

这是款有趣的挂钟，以沙丁鱼罐头为外观设计，里面的沙丁鱼甚至还可以摆动，对了，那就是挂钟的钟摆。

Officials from Greenwich Observatory have the clock checked twice a day. On the B.B.C you can hear the clock when it is actually striking because microphones are connected to the clock tower.

格林维治天文台的官员们每天两次派人矫正此钟，当大钟打点的时候，你可以从英国广播公司的广播中听到，因为钟塔上接了麦克风。

Digital Clock is using assembly language to achieve, and it is a clock on the revised procedures.

数字时钟也是用汇编语言实现的，是上一个时钟程序的改版。

It's definitely unique and eye-catching clock which literally tells you the time unlike your standard digital clock.

这绝对是独特的和引人注目的时钟频率，这从字面上告诉你的时间不同，您的标准数字时钟。

Clock main mode can be replaced by an analog or digital clock skin show city information.

时钟主要模式可以取代模拟或数字时钟显示，城市信息化的皮肤。

In this trend, digital clock, multifunction clock has become the modern design of the production of research-led direction.

在这种趋势下，时钟的数字化、多功能化已经成为现代时钟生产研究的主导设计方向。

And by comparing the actual clock, find out the source of the error and determined the method of adjusting error, reduce errors as much as possibly, so this system can achieve a practical digital clock with error within the permissible range.

并且通过对比实际的时钟，查找出了误差的来源，确定了调整误差的方法，尽可能的减少误差，使得系统可以达到实际数字钟的允许误差范围内。

7 To 3.3 V operating supply voltage 44.1 kHz sampling frequency 16.9344 MHz (384fs) system clock Built-in crystal oscillator circuit 16-bit, MSB rst, rear-packed serial data input format ( 64 fs bit clock) 8-times oversampling digital lter · 32 dB stopband attenuation ·+0.05 to -0.05 dB passband ripple Deemphasis lter operation · 36 dB stopband attenuation ·-0.09 to +0.23 dB deviation from ideal deem- phasis lter characteristics Attenuator · 7-bit attenuator (128 steps) set by microcontrol- ler Soft mute function set by parallel setting ·(approximately 1024/fs total muting time) Mono setting · Left or right channel mono selectable by micro- controller Built-in innity-zero detection circuit , two-channel D/A converter · 3rd-order noise shaper · 32fs oversampling Built-in 3rd-order post-converter low-pass lters 24-pin VSOP package Molybdenum-gate CMOS process

2.7至3.3 V工作电源电压为44.1千赫的采样频率16.9344兆赫（384fs）系统时钟内置晶体振荡器电路的16位，MSB在前，后包装的串行数据输入格式（64飞秒位时钟）8倍超采样数字滤波器·32分贝的阻带衰减·+0.05至-0.05分贝通带纹波去加重滤波器的运作·36 dB抑制频宽衰减·-0.09到0.23 dB的偏差认为不理想，症状困扰评估滤波特性衰减器·7位衰减器（128级）集由单片机在-莱尔软静音功能的平行设置·（共约1024/fs静音时间）单声道设置·左或右声道单声道微控制器可选的内置的无限零检测电路Δ，两通道的D / A转换器·第三阶噪声整形·32fs过采样内置三阶后转换器的低通滤波器24引脚VSOP封装钼栅CMOS工艺

The company has development, production and sales: craft wood quartz clock series, mechanical floor clock calendar series and digital information products, combined with Flash, artistic lamps draw, draw light into one advertisement.

公司先后研制、生产和销售：木质石英工艺钟系列、机械落地钟系列及数码信息历系列产品，结合动感画、艺术灯画、广告灯画为一体。

And by comparing the actual clock, find out the source of the error and determined the method of adjusting error, reduce errors as much as possibly, so this system can achieve a practical digital clock with error within the permissible range.

并且通过对比实际的时钟，查找出了误差的来源，确定了调整误差的办法，尽可能的减少误差，使得系统能达到实际数字钟的允许误差范围内。

" I' d like to get some rough idea about music in the baroque ear, please."

请简要介绍一下巴罗克时期的音乐，好吗？

The results showed that the peak latency and pattern of SEPs elicited by electrical needling in LI-l1 and MP were similar. The amplitude of SEPs elicited by electrical needling in LI-l1 was higher than that of MP. There was no obvious SEPs generation when MM was electrical needling.

结果显示，电针刺激曲池穴和其邻近桡侧伸腕长肌运动点诱发性脑电波的波形和波峰时间是类似的，只是穴位的诱发性脑电波波幅较大，而电针刺激非穴位点并没有明显的诱发性脑电位。