查询词典 digital channel

The paper expands some important links of the communications system which include channel, noise, digital transmission of analog signal, channel encode and signal modulation.

本文在深刻理解通信系统理论的基础上利用MATLAB强大的仿真功能，设计了许多具体的通信系统仿真模型。

Liu Jiang east: During the sale with regular product, beijing east the sale price of product of store home appliance is lower than traditional channel 10%, the price of digital product is lower than traditional channel 15%.

刘强东：在产品正常的销售期间，京东商城家电产品的销售价格比传统渠道低10%，数码产品的价格比传统渠道低15%。

Double channel bandpass sampling method for wide band IF signal is presented to settle the problem of blind zone,which exchanges one more sampling channel for simplification of clock circuit and band pass filter.As a practical reconnaissance receiver, real-time processing performance must be considered.Digital channelizing method lays the base of parallel processing by multi DSP chips and discarding of the redundant data resulting from double channel bandpass sampling.

针对带通采样存在着频率覆盖盲区的问题，提出了宽带中频信号双通道带通采样的方法，通过增加一个采样通道既解决了传统处理盲区方法中设计复杂采样时钟电路、高矩形系数滤波器的困难，还缓解了后续DSP处理压力。

In the same time, kinds of digital detection methods in optical recording PR channel are also discussed and codes in optical PR channel are surveyed.

同时，对高密度下的各种数值检测方式进行了比较，并探讨编码在光记录部分响应通道中的应用。

On the basement of passband subsampling and digital downconvertion, according to QPSK with 30M carrier frequency and 8M bandwidth, digital IF channel is elaborately analyzed .In this module, multiple phase filters are elaborately designed .According to this module, IF digital signal is simulated .

以对中频为30MHz，带宽为±4MHz的输入QPSK信号进行带通欠采样和数字下变频为基础，提出和分析了中频数字化通道的实现方案，进行了相应的多相低通抽取滤波器的设计，并针对数字中频信号就数字下变频模块进行了仿真，从而验证了整个下变频系统参数设计的可行性。

Having studied the digital down-conversionprocess of IF signal before the base band process which follows A/D conversion in wireless communication,the paper puts forward a new idea of utilizing the FPGA to realize multi-channel digital signal DDC.Through analyzing the features and performances of CIC filters,HB filters and multiphase-filter,we combine them with decimators and decimate the A/D data,thus reducing the digital signal rate and the load of DSP when processing the base band signal.

软件无线电技术是在通用的开放式无线电智能平台上，通过安装不同的软件来完成各种通信功能，其结构的基本特征之一就是使A/D变换尽量靠近射频端，目前的方案是在中频对模拟信号进行数字化，对中频数字信号进行下变频处理，使数字信号量降低到高速DSP能够处理的程度[1]。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

The paper investigates both block-type pilot linear minimum mean square error algorithm and IEEE802.16 OFDM channel estimation analysis. Simulation results confirm the block-type pilot structure is more suitable for IEEE802.16 system. An optimal pilot setting algorithm, based on space frequency domain, is explored and the pilot chart is presented. The proposed algorithm finds its application in MIMO-OFDM. Simulation results show the algorithm presents a good approximation to the perfect channel state information curve, with about 2dB difference in SNR. The simulation results also demonstrate the algorithm achieves fairly high stability in the environment of fast fading, performance of the proposed algorithm is better that of pilot training channel estimation.3. Taking into account the characteristics of IEEE802.16 OFDM system, OFDM system simulation platform is constructed in Matlab, exploiting simulink as a tool. OFDM modulation and demodulation simulation system are configured on LabVIEW platform. All the system signal processing is simulated, including defining system parameters, designing modulation model, and verifying all the proposed algorithms under different environments, such as white Gaussian noise, multi-path fading, with or without guard interval etc. Bit error performance is evaluated. The research provides valid theoretical basis for practical OFDM system performance evaluation.4. Taking advantage of software radio, the paper designs a hardware platform with both 256-IFFT/FFT and 512-IFFT/FFT OFDM schemes co-existing in one platform. You can predetermine one from the two schemes to carry out almost the same model function with different system performance and parameter setting.5. Referring to IEEE802.16 standard, the paper proposes a design method for generating signals and frames suitable for laboratory investigations implemented in laboratory environment.6. Based on 6701evm digital evaluation card, combined with analogy front-end, the paper designs a DSP software model to deal with baseband signal processing. An overall OFDM scheme, with modulation and demodulation function, is accomplished.

讨论分析了MIMO-OFDM中一种基于空频域的最优导频设置算法，给出了导频图案，通过仿真实验表明，该算法与理想的信道状态信息曲线非常接近，信噪比差距约在2dB左右，并且在快衰落条件下具有较好的稳定性，其性能要优于基于前导训练的信道估计方法。3、根据IEEE802.16OFDM系统特点，论文分别在Matlab中应用Simulink工具构建OFDM系统仿真平台、在LabVIEW平台上实现了OFDM调制解调仿真系统，模拟了整个系统的信号流程，进行了OFDM仿真系统参数的选择和调制模块的仿真设计、论证各算法性能，并根据各种不同的条件：例如高斯噪声、多径衰落、有无保护间隔等，对系统的误码特性进行了评估，为正确评价实际OFDM系统的性能提供了有效的理论依据。4、论文以软件无线电思想作为指导，提出了以256点IFFT／FFT为核心和以512点IFFT／FFT为核心的两种OFDM算法模式并存于同一个硬件平台、且可预选的方案，它们在参数选取和性能指标上有所差异，均实现了相似的模块和功能。5、论文参考IEEE 802.16无线网络标准的参数设置，针对本设计系统的应用环境和系统硬件的性能速率，提出了一种应用于实验室环境的信号结构、帧格式等参数设计。6、论文基于TI公司的6701evm数字评估板卡，结合模拟前端搭建数字中频平台，设计了基带处理的DSP软件模块并进行系统调试，基本实现了一套完整的OFDM调制解调方案。

Its final target is to fully digitize the analogue receiver. The all digital receiver not just means digitizing every unit of the analogue receiver, but is a new receiver architecture. The two outstanding characters of this new architecture is: 1 It uses a high stable oscillator to generate a fixed frequency source. And both the sample signal and the local carrier required are obtained from it. 2 Once the received signal has been sampled by a high speed A/D converter, some digital signal processing algorithms will be used to realize all further processes, such as digital down-converting, match filtering, symbol timing, channel equalizing, carrier synchronizing, demodulating and decoding.

全数字接收机并不是简单地将传统的模拟接收机中所有的部件数字化的结果，而是一种全新的接收机体系结构，这种新的体系结构具有两个最为突出的特点：1）采用高稳定度晶体振荡器产生一个固定的本地频率源，接收机中所需的采样时钟信号和本地载波均从这一固定频率源得到；2）接收信号一旦经过高速模数转换后，余下的工作如频率变换、匹配滤波、定时同步、信道均衡、载波同步、符号解调、判决与译码等全部由数字信号处理算法来实现。

This brought fixed cost, but it also is meant at the same time use a source to won't make you singlehanded assume a problem.

这带来了一定的成本，但它同时也意味着使用开源不会让你独力承担问题。

He gained a small fortune in real estate.

他在房地产上发了一笔小财。