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digit circuit相关的网络例句

查询词典 digit circuit

与 digit circuit 相关的网络例句 [注:此内容来源于网络,仅供参考]

A combinational circuit that has three inputs that are an augend, D, an addend, E, and carry digit transferred from another digit place, F, and two outputs that are a sum without carry, T, and a new carry digit, R, and in which the outputs are related to the inputs according to the following table.

一种组合电路,有三个输入端和两个输出端;三个输入端是:被加数d、加数e以及从另一个数位传来的进位数f;两个输出端是:无进位和数t及新的进位数r。电路的输出和输入的关系如下表所示

It simulates the circuit breaker with a zero impedance branch, and adopts the linear network characteristic and theory, variable structure and variable parameter analyses to transfer the short-circuit current flow in the bus-bar equality into each side of circuit breaker, and deduces the sequence component model and algorithm for calculating the short-circuit current of circuit breaker when the short-circuit fault occu...

该方法将断路器作为一条阻抗为零的支路来模拟,运用线性网络特性、定理及变结构与变参数的分析方法,将母线上短路时的短路电流等值转移到断路器两侧,导出了相当于在断路器两侧分别发生短路故障时,流过断路器的短路电流的序分量模型和算法。

With this mode of working the base-emitter circuit is the input side;and the emitter through base to collector circuit the output side.although these have a common path through base and emitter, the two circuit are effectively separated by the fast that as far as polarity of the base circuit is concerned,the base and upper half of the transistor are connected as a reverse biased diode.hence there is no current flow from the base circuit into the collector circuit.

这一工作模式下,基极-发射极电路是输入端,发射极通过基极,再到集电极电路的输出端。虽然它们都有一个共同的路径通过基极和发射极,这两个电路是通过和基极电路相关的尽可能的有效快速分离开的,基极和基极以上的一半以上的晶体管作为一个反偏二极管与之相连接。

Thereinto,the measuring circuit is composed of heating circuit, voltage follower circuit, warning circuit, gas sensor failure indication circuit and power supply indication circuit;The microprocessor adopts 8051 Single - Chip computer;The LED adopts Seven LED figures display;The keyboard adopts separate type non-coding keyboard.

其中测量电路由加热电路、电压输出电路、报警电路、气敏元件损坏指示电路和电源指示电路组成;微处理器采用8051单片机;LED显示采用七段LED数码显示器;键盘采用的是独立式非编码键盘。

To solve the problems of the limescale ,the oxidation which are produced by the direct contact between a metallic conductor and water, the detecting reliability and the service life, the utility model adopts the technical proposal as below: the proposal comprises a monostable controllable trigger, a second low-pass filter, a voltage follower and a display circuit, the power circuit links with the monostable controllable trigger, the second low-pass filter, the display circuit and a timebse pulse circuit separately, the utility model is characterized in that the monostable controllable trigger, the second low-pass filter and the display circuit sequentially links, the monstable controllable trigger separately links with a water lever sensor and the timebase pulse circuit.

为了解决金属导体与水直接接触会产生水垢和氧化,影响检测可靠性和使用寿命的问题,本实用新型采用了以下技术解决方案:它包括单稳可控触发器,二阶低通滤波器,电压跟随器和显示电路,电源电路分别与单稳触发器,二阶低通滤波器,显示电路和时基脉冲电路相接,其特征在于单稳可控触发器,二阶低通滤波器,电压跟随器和显示电路依次相接,单稳可控触发器分别与水位传感器和时基脉冲电路相接。

To solve the problems of the limescale ,the oxidation which are produced by the direct contact between a metallic conductor and water, the detectingreliability and the service life, the utility model adopts the technical proposal as below: the proposal comprises a monostable controllable trigger, a second low-pass filter, a voltage follower and a display circuit, the power circuit links with the monostable controllable trigger, the second low-passfilter, the display circuit and a timebse pulse circuit separately, the utility model is characterized in that the monostable controllable trigger, the second low-pass filter and the display circuit sequentially links, the monstable controllable trigger separately links with a water lever sensor and thetimebase pulse circuit.

为了解决金属导体与水直接接触会产生水垢和氧化、影响检测可靠性和使用寿命的问题,本实用新型采用了以下技术解决方案:它包括单稳可控触发器、二阶低通滤波器、电压跟随器和显示电路,电源电路分别与单稳触发器、二阶低通滤波器、显示电路和时基脉冲电路相接,其特征在于单稳可控触发器、二阶低通滤波器、电压跟随器和显示电路依次相接,单稳可控触发器分别与水位传感器和时基脉冲电路相接。

The high-power system including main circuit, the charging and discharging circuit of synthetic circuit test system, and the principle of charging and discharging for current supply using electrolytic capacitor is presented. At the aspect of circuit breaker control, the advanced permanent magnetic actuator is used and analyzed in this paper, including the precision computation and using in synthetic circuit. The trigger circuit of voltage supply is designed, and the intelligent control is used to trigger the igniting gap. And the integraph based Rogowski coil is designed and employed the intelligent detection of breaking current.

强电系统介绍了合成回路试验系统的主电路及其充放电电路,讲述了电流源采用电解电容器的充放电原理;断路器控制方面,采用当前比较先进的永磁操动机构,并对永磁机构的原理、精度计算和在合成回路中的应用做了详细地分析;设计并制作了电压源点火回路,对球隙点火进行智能控制;在智能检测开断电流方面,设计并制作了与Rogowski线圈相配合的积分器。

Electrical system and support the main circuit when the circuit is also linked to separate with a painting in the drawings and paintings in the main circuit general auxiliary circuit to the left or above, the main circuit with pachytene, assisted by the thin circuit portrayed.

电气系统的主电路与辅助电路时既分开又有联系地画在同一张图纸上的,主电路一般画在辅助电路的左侧或者上面,主电路用粗线,辅助电路用细线描绘。

The chip consists of a power mos, mode select circuit, driving circuit, and two series of controller circuit. The controller consists to the active current sensing circuit, sample and hold circuit, hysteresis current comparator, voltage to current converter, error amplifier and non-overlap circuit.

晶片包含一组功率电晶体、模式选择电路、驱动电路及二组控制电路,控制电路主要架构有主动式电流感测电路、取样保持电路、磁滞电流比较电路、电压对电流转换电路、误差放大器及非重叠电路。

The high speed multiplex first-in first-out storage structure includes at least two memory unit arrays, one integrated decoder circuit between the two memory unit arrays, one write-in control circuit over the decoder circuit, one read-out control circuit below the decoder circuit, two data buffers on the two memory unit arrays separately, two multiplex circuits and two output circuits below the two memory unit arrays separately, and one write-1 clock buffer and one read-out clock buffer over and below the decoder circuit separtely.

一种高速多路先进先出存储器结构,包括一至少两存储单元阵列、一位于至少两存储单元阵列中间的整体解码电路、分别位于整体解码电路的上下的一写入控制电路及一读出控制电路、分别位于至少两存储单元阵列上的两数据输入缓冲器以及依序位于两存储单元阵列下的两多工电路及两输出电路,在整体解码电路的上下分别设置一写入时钟缓冲器及一读出时钟缓冲器。

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