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decimator相关的网络例句

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与 decimator 相关的网络例句 [注:此内容来源于网络,仅供参考]

The main improvement in this thesis is focused on the high order FIR filter of decimator.

而最主要的改良是在於里头的高阶有限脉冲响应滤波器。

This dissertation complete all the steps of the design and implement of decimator, and prove the possibility and flexibility of using FPGA to realize decimator both in theory and in practice.

本文完整地完成了抽取器的设计和实现过程,从理论到实际硬件一步步验证了FPGA技术应用于抽取器的可行性及灵活性。

A future column will examine how the modulator, digital/decimator filter, and adjustable decimation ratio work.

未来的窗将检测调节器、数字/抽取滤波器和可调节抽取比例怎样工作。

At last, this design of the decimator is implemented on FPGA hardware platform, and tested by oscilloscope and spectrum analyzer.

最后,采用系统硬件平台将程序写入FPGA芯片,利用示波器和频谱分析仪对设计的抽取器进行了频域和时域性能分析。

In the digital part, the algorithm of the decimator is discussed including the comb filter and the finite impulse response filter.

在数位方面探讨的是降频数位滤波器的演算法设计,包含了梳型滤波器以及有限脉冲响应滤波器。

The small area decimator for programmable oversampling ratio SDM A/D converters is designed and implemented.

在此,一个针对可变超取样率三角积分类比数位转换器的低面积降频器被设计与实现。

THE DESIGN AND IMPLEMENTATION OF DECIMATOR BASED ON FPGA ABSTRACT Software radio is regarded as the developing direction of communication in future, and as one part of this, decimator change the high rate dataflow to a lower one, which meets the require of real-time processing and makes software radio come true.

软件无线电是未来通信的发展方向,而作为其重要组成部分之一的抽取器,将难以实时处理的高速数据流变为低速率信号,使软件无线电的实现成为可能。

The designers of the VT-49 Decimator have stated that the ship was created as an "evil" Imperial version of Millennium Falcon .

在幕后,VT - 49 Decimator"被害者"级攻击及运输船的设计师指出,设计船的目的是为了创创造一个"邪恶"的、帝国版本的"千年隼"号。

As a result of half registers requirement, the 24.6% area reduction for high order (126th-order) FIR filter is obtained, which result in 15.8% area reduction for the 4-stages decimator (20.9% area reduction for 3-stages decimator).

由於只需使用一半的储存元件,本架构相对於直接结构摺叠架构而言,可使降频器里的高阶有限脉冲响应滤波器减少24.6%的矽面积,进而达到整体使用四个阶段降频器15.8%的面积节省(对於三个阶段降频器,整体面积则可减少20.9%)。

The process of creating a DSD signal is conceptually similar to taking a 1-bit delta-sigma analog-to-digital converter and removing the decimator which converts the 1-bit bitstream into multibit PCM.

过程中创造一个信号,渠务署,是在概念上相似,以1位Δ-Σ模拟到数字转换器,并消除decimator转换1位码流成多位的PCM 。

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