查询词典 database access

A correlation system for Time Division Multiple Access positioning systems is disclosed, whereby a position receiver acquires, tracks, and demodulates a plurality of Code Division Multiple Access modulated positioning signals are pulsed in a Time Division Multiple Access scheme.

公开了一种用于时分多址定位系统的相关系统，借助该系统，定位接收机可以捕获、追踪和解调多个在时分多址方案中被脉冲化的码分多址调制的定位信号。

In order to satisfy the requirement of various space mission simulations and analysis, a standard interface and common service for access to the system resources, that is, resource access protocol, is designed, thus the independencies of resource storage manner and resource representation are realized. The design of resource access protocol introduced the object-oriented hierarchical method.

结合航天任务的仿真和分析对资源管理的要求，总结出资源管理系统应具备的功能和特点；从对分布式仿真资源进行高效管理和使用的角度着手，提出了基于代理的系统构建方式；进而设计了资源管理系统的体系结构，并分别探讨了体系结构的四个层次：基础资源层、通用操作环境、仿真应用接口层和管理控制层。

Brewster Kahle launched the Internet Archive in 1996. From the start it provided Open Access to its mirror of the historical Internet as well as to many special collections.The Internet Archive sponsors the Open Access Text Archive, Ourmedia (http://ourmedia.org/), and the new Open Education Resources project, and cosponsors the Open Access Million Book Project with Carnegie Mellon University.

2.1996年布鲁斯特·卡利建立了互联网档案，从此它提供了开放近用的历史档案如许多典藏，互联网档案主办机构赞助开放近用典藏，Ourmedia( http：//ourmedia.org/)，和新的开放教育资源项目，并且与卡内基梅隆大学共同赞助对一百万本书采开放近用计画。

To overcome the shortcoming of the double-way authentication access control scheme based on Harns digital signature, a new double-way authentication protocol is proposed to improve the old one. A new single-key-lock-pair access control scheme is proposed as a improved access control scheme, based on the property that a integer can be denoted into only one binary digital.

针对基于Harn数字签名双向认证访问控制实现方案中所存在的问题，运用密码技术改进了原方案的双向认证协议，并作为对原访问控制方案的改进，基于整数二进制表示的唯一性，提出了一种新的单钥-锁对访问控制方案。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

There is daytime access to our award-winning library; research resources include access to other University of London libraries, the British Library and the British Museum; research students are eligible to apply for an Overseas Research Student award; a number of College studentships for doctoral and research students are also available; research students and their supervisors meet at mutually convenient times; many programmes have evening tuition, leaving the day free to combine directed study with other activities; full computing facilities and support; access to University of London accommodation services; College located at heart of academic London, 5 minutes from the British Museum.

设施白天学生可使用位於校内且曾荣获殊荣的图书馆，可用的研究资源还包括所有伦敦大学的图书馆，大英图书馆和大英博物馆；研究生皆有资格角逐海外研究生奖和奖助学金。研究生与他们的助教定期碰面；许多课程有晚间的加强辅导，白天则可运用於上课和其他的活动。学生有权使用伦敦大学的住宿服务和完备的电脑设备与协助。学校位於伦敦学术中心，距大英博物馆仅五分钟距离。

Therefore at present the theory of acyclic database schema design has become a new important branch of database study.

无环数据库模式的设计理论研究，已成为了当前数据库研究的一个新的重要分支。

Combining the database and graph theory put the theory of acyclic database schema forward.

数据库理论与图论的结合产生了无环数据库模式设计理论。

Detail the aip aps to use the database, know how to learn, and must know the benefits of the database, it will help you learn faster.

详细说明：详细讲述了aip aps数据库的使用方法，懂得学习的人一定知道数据库的好处，它会帮助你更快的学习。

We got alerted a couple of times while we were down south that HETs were on the way to bring us back up north because things were going to go hot again, but it was just rumors.

南下的途中我们不只一次得到警告说重型装备运输车将拉着我们重新北上，因为局势正在变得重新紧张起来，但这只是谣传。

It's the one where they find the ghost in the salt mine.

这一集是演他们在盐矿找到鬼