查询词典 data switching

A method is provided for encoding and decoding a sequence of digital data, according to which a portion of the sequence of digital data corresponds to a data block that includes several data packets, at least two data packets per data block containing an identifier. The position of the data packet within the corresponding data block can be determined based on the identifier, and the data is encoded or decoded by taking into account the identifier.

本发明给出了一种用于对数字数据序列进行编码和解码的方法，其中该数字数据序列的一部分相当于一个数据块，其中该数据块包含多个数据包，其中每个数据块的至少两个数据包分别包含一个特征标记，其中根据该特征标记确定数据包在所属的数据块中的位置，以及其中在考虑该特征标记的情况下对数据进行编码或解码。

The method includes establishing one reverse mapping list comprising list items; reading the mapping data recorded in the data block state list item area to the list items during system initialization; checking reverse mapping list and finding the data block in Flash memory during reading some logic block; and writing the updated data into the empty data area of one new data block, writing the mapping data between the new logic block and the new data block into the state list item area and updating the mapping data of the corresponding list item in the reverse mapping list during writing some logic blcok.

包括：建立一个由表项组成的反向映射表，一个表项对应一个逻辑块；在系统初始化过程中，将数据块状态表项区中记录的映射信息，按逻辑块号与表项间的对应关系读取到各表项中；读取某逻辑块时，以其逻辑块号作为表项索引查找反向映射表，定位到表项，根据表项中记录的映射信息，在Flash存储器件中查找到数据块；写入某逻辑块时，将更新数据写入一新数据块的空白数据区中和将该逻辑块与新数据块间的映射信息写入状态表项区中，同时更新反向映射表相应表项的映射信息。

This invention discloses one data regroup method, which is based on the original independent and redundant RAID system high address to preserve one block disk space as regroup area and to repeat the following steps: a, determining the current regroup data low address and to regroup the data from high address to low address into new RAIN type of data; writing the regroup data from initial address into the new RAID type data; using the current regroup data of low address as the next regroup data high address as the next second initial address of the data.

本发明公开了一种数据重组方法，在原独立冗余磁盘阵列系统高地址侧尾部预留一块磁盘空间作为重组区域，将该预留重组区域的高地址作为写入数据的起始地址，并将原RAID系统中存有数据的高地址作为重组数据的起始高地址；数据重组完之前重复执行以下步骤：确定当前要重组数据的低地址，并将当前要重组数据高地址到低地址之间的数据重组为新RAID类型数据；将重组后的数据从写入数据的起始地址向低地址方向，顺序写入新RAID系统中；当前要重组数据低地址的邻接低地址作为下次要重组数据的高地址，当前写入数据低地址的邻接低地址作为下次写入数据的起始地址。

The main features of this paper is: nothing to do with the platform, this system can be compatible with the majority of software and hardware used by the platform, as well as various database platform, shielding the differences of hardware and software platform such as network, operating systems, databases, application systems and so on, so that enterprises and institutions could achieve seamless, transparent data exchange through data exchange system; Java technology used to develop the system transplantability; using data exchange center to achieve centralized data processing, different data format conversion, increased system scalability; from data transmission, authentication, access control, encryption and more news content log-class areas enhanced data exchange system security; using DES and RSA algorithm , increased the confidentiality of data transmission; create WrapperTimer category achieved data transmission timing implementation and reduce the dependence on artificial.

设计的系统与平台无关，能兼容企业所用的大多数软硬件平台，以及各种数据库平台，屏蔽网络、操作系统、数据库、应用系统等软硬平台的差异，使企事业单位通过数据交换系统实现无缝的、透明的交换数据；采用数据交换中心来实现数据的集中处理、不同数据格式的转换，增加了系统的可扩展性；从数据传输、身份认证、权限控制、消息内容加密和多级日志等多方面增强数据交换系统的安全性；用DES和RSA算法对XML文件或XML文件中的元素进行加密，增加传输数据的保密性；创建WrapperTimer类实现了数据传输的定时执行，降低了对人工的依赖性。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

This invention relates to a structuring method for a multi-allotter front end system of a cluster server characterizing in including the following steps: setting up more than two front end allotters matched with two net cards, a cluster server front end system of a collecting tray, the data input end net cards of the front allotter are cascade via the collecting tray, the data output end net cards of all front allotters are connected with the switching device of the cluster server back end system, the data input end net cards are matched with a same virtual IP, all input data packets are transmitted to all front end distributes in broadcast way, every front server computes, the input data packet IP addresses or TCP port number in hash to decide if said data packet is processed.

本发明涉及网络服务器技术领域，尤其是一种集群服务器的多分配器前端系统构成方法，其特征在于：包括以下步骤，建立包括两台及以上的配置了两块网卡的前端分配器、一台集线器的集群服务器前端系统，所有前端分配器的数据输入端网卡通过集线器并行集联，所有前端分配器的数据输出端网卡与集群服务器后端系统的交换机相连；所有前端分配器的数据输入端网卡配置一个相同的虚拟IP；通过集线器将输入数据包以广播方式传输到所有前端分配器；各前端分配器对输入数据包IP地址或TCP端口号进行散列计算，决定是否处理该数据包。

The converter combines the advantages of the PWM technique and soft-switching technique, the PWM is effected all over the whole loads range, and soft-switching is effeted only in the switching transition period, the ZVS of leading-leg is achieved by using the energy stored in leakage inductor of the transformer and the output inductor, the ZCS of lagging-leg is achieved by using a blocking DC capacitor, the ZVS and ZCS are achieved for the whole load ranges (5A~250A).

控制电路采用相移控制方式，综合了PWM控制和软开关技术的优点，在大范围内实现PWM控制，而在功率器件换流期间实现软开关换流，其中超前桥臂利用变压器的漏感，实现了零电压开关，滞后桥臂利用隔直电容，实现了零电流开关，并且整个变换电路能在（5A~250A）的范围内实现软开关工作条件，满足弧焊电源负载变化大的特点。

Later, it makes some comparison with four kinds of modulation technique, and finally, it implements the three-level PWM switching power amplifier with the PWM technique. The power of the amplifier is 2kVA, and the frequency bandwidth is 10～3kHz. In the thesis, the author designs and makes the hardwares of the switching power amplifier. The hardwares contain power inverter rank circuit, control system circuit based on DSP, drive and isolation circuit, and protective circuit. The thesis also analyses the potential safety problems and put forward some solutions for the problems. Furthermore, the thesis accomplishes the software design of the control system, and successfully debugs it. The methods of designing higher power ampilfier are also discussed in the thesis. It analyses the feasibility of the methods, outlines the way of how to design higher power switching power amplifier, and does some experiments with the method of switches-parallelling.

根据电动振动试验系统对开关功放的要求，提出了以电感电流瞬时值控制技术为基础的三电平脉宽调制开关功放的设计方案，并通过系统仿真进行了原理性论证；然后设计并制作了开关功放的硬件，包括功率转换电路，基于DSP的控制电路，驱动、隔离电路以及保护电路；针对开关功放数学模型不易得出的特点，细致分析了模糊自适应PID控制方法，在此基础上编写了控制程序；研制出一台功率为2kVA，通频带为10～3kHz的三电平脉宽调制开关功放；论文中还探讨了实现大功率开关功放的方法，分析了各种方法的可行性，给出了实现大功率开关功放的思路，并进行了并联开关管实现大功率开关功放的实验。

A novel phase-shifted zero-voltage and zero-current switching PWM DC/DC full-bridge converter is presented in this thesis, which is based on the groundwork of summarization of the development of Power Electronics in recent years and lucubration in theoretical basis of modern high frequency soft switching power convert technique and analysis of operation principle, characteristic of the circuit and inherent drawbacks of the traditional phase-shifted zero-voltage switching PWM DC/DC full-bridge con...

本文在对近年来电力电子学科的发展高度综述和对现代高频软开关功率变换技术理论基础深入研究的基础上，对传统的移相控制ZVS PWM DC／DC全桥变换器的工作原理、电路特性、存在的缺点进行了分析，在此基础上提出了一种改进型的移相控制ZVZCS PWM DC／DC全桥变换器。

Although translator has turned from being a crystal ball by which the original culture can unrestrainedly penetrate to another crystal ball by which the target culture can freely traverse, the translator's personal embodiment, in the process of cognitive act, are still absent in translation studies. Translators are still subjects without body or simply disembodied subjects.

译者虽然由原语文化可以自由穿透的玻璃球变成了译语文化可以自由穿越的玻璃球，但译者认知过程中的个体体验在翻译研究中依然缺席，译者依然仅仅是一个没有躯体体验的主体。

Chillingly, he claimed our technology is 'not nearly as sophisticated' as theirs and "had they been hostile", he warned 'we would be been gone by now'.

令人毛骨悚然的，他声称我们的技术是'并不那么复杂，像他们一样，和"如果他们敌意"，他警告说，'我们将现在已经过去了。