查询词典 data bus

Port 0 is the multiplexed address/data bus.

端口0是复用地址/数据总线。

The thesis' content is modelling and analysis of integrated avionics system data bus with Stochastic Petri Net.

本文的内容是基于随机PETRI网的航空电子综合系统数据总线的建模分析。

SAK-C167CR-LM easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave BUSY and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 3.3V (0.3V) power supply Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP Industrial temperature range (-40C to +85C) is available for selected speeds

朔C167CR - LM滚动轻松扩展数据总线的宽度为32位或更多的使用主/从选择当级联多个器件M / S的=关于硕士M / S的=忙输出标志VIH VIL数值就投入繁忙和忙碌的奴隶中断标志片全部港口的仲裁逻辑芯片上的信号灯的信号港口之间的异步操作完全由硬件支持任何港口的LVTTL兼容，（为0.3V）电源可在84引脚PGA的，84引脚PLCC和单3.3V 100引脚TQFP工业温度范围（- 40C至+85 C）是选定的速度可

MBRD1035CTLT4G easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave BUSY and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 3.3V (0.3V) power supply Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP Industrial temperature range (-40C to +85C) is available for selected speeds

1第1页，本页显示记录1-11，共11条记录分1页显示MBRD1035CTLT4G轻松扩展数据总线的宽度为32位或更多的使用主/从选择当级联多个器件M / S的= VIH对奴隶繁忙投入繁忙和中断标志对主M / S的= VIL数值忙输出标志上港口全部仲裁逻辑芯片的片上信号信号港口之间的异步操作完全由硬件支持任何港口的LVTTL兼容，（为0.3V）电源可在84引脚PGA巡回赛，84引脚PLCC和100引脚TQFP封装3.3V单工业温度范围（- 40C至+85 C）是选定的速度可

Since the longest codeword is 24 bits,32-bit data bus is used to reduce the scale of circuit.

由于比特流中最长的码长为24比特，故采用32位的内部总线结构，减小了电路规模。

We complete the design of crossbar switch with 6 ports and 32 bits data bus on one chip of FPGA.

我们在单片FPGA中完成了6个端口、32位数据总线宽度交叉开关的设计。

Advanced aircraft power system and its control system was introduced and fault tolerant design of data bus was discussed.

介绍了先进飞机供电系统及其控制系统的组成，并对数据通信总线的容错设计进行论述。

Each of the first and second processing units has a respective first output data bus.

每个所述第一和第二处理单元具有相应的第一输出数据总线。

Another alternative is to directly connect the converter to the processor's data bus.

另一种选择是直接将转换器与处理器的数据总线相连。

The data that comes back from sensor feedback repeats on other data bus line carry out, this process and written process are coinstantaneous.

从传感器反馈回来的数据在其他的数据总线上几回执行，这个历程和写的历程同时发生。

The absorption and distribution of chromium were studied in ryeusing nutrient culture technique and pot experiment.

采用不同浓度K2CrO4(0，0.4，0.8和1.2 mmol/L)的Hoagland营养液处理黑麦幼苗，测定铬在黑麦体内的亚细胞分布、铬化学形态及不同部位的积累。

By analyzing theory foundation of mathematical morphology in the digital image processing, researching morphology arithmetic of the binary Image, discussing two basic forms for the least structure element: dilation and erosion.

通过分析数学形态学在图像中的理论基础，研究二值图像的形态分析算法，探讨最小结构元素的两种基本形态：膨胀和腐蚀；分析了数学形态学复杂算法的基本原理，把数学形态学的部分并行处理理念引入到家实际应用中。