查询词典 data bus

The system address bus and data bus chip.

3系统地址总线和数据总线芯片。

The system bus is divided into three logical functions; the address bus, the data bus and the control bus .

系统总线的功能在逻辑上被划分为三部分：地址总线、数据总线和控制总线。

The DM642 External Memory Interface expands two pieces of MT48LC4M32B2 (4M*32 bit SDRAM) and a AM29LV33C (8M bit FLASH). SDRAM is connected to the 64bit data bus of EMIF, can read/write 64bit data at every cpu cycle, be used to store program, data and image.

单片机采用了Cygnal公司的C8051F020，它使用了CIP-51微控制器内核，与MCS-51TM指令完全兼容。C8051F020通过I2C总线和通用I/O口与DM642相连接，接收I2C偏差数据，并通过单片机内部的两个全双工UART输出。

In the M51954AFP, when MRD = 1, it enables the three-state bus drivers (DB0-DB3) and transfers data from the DATA-IN lines onto the data bus.

在M51954AFP，当MRD的= 1，它使三态总线驱动程序（DB0 - DB3小波），从数据中的数据总线上传输数据。

Ethernet data stream with HTML format and DVB-C data stream with MPEG2 format is inputted in form of ASI and SPI, and send it into FIFO via 74F675A. 5416 packs and encrypts and transfers to DVB-C and Ethernet by time diplex mode. Thereby, data bus access is realized.

HTML格式以太网数据流和MPEG2格式DVB-C数据流以ASI和SPI形式输入，经74F675A串并转换进入FIFO.5416进行打包和加密并以时分复用方式传输DVB-C和以太网数据，实现数据总线访问。

Theoretically,system memory bus with a speed of 66 MHz and a 64-bit data bus bandwidth can move 528 megabytes of data per second maximum(66 megacycle/sec*64 bits*1 byte/8 bits=528MB/sec).

在理论上，66MHz 速度的系统存储总线加上64位数据总线带宽，一秒钟内最多可传送528兆字节的数据。

Big-Endian ConfigurationA signed byte load expects data on data bus inputs 31 through to 24 if the supplied address is on aword boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on.

大尾段配置阿签署字节负载预计在31日的数据总线输入数据，如果通过向24所提供的地址上的字的边界，数据总线投入23日至16如果它是一个字地址加上一个字节，依此类推。

For example, if a register isconnected to the data bus in an 8-bit machine. eachline of the bus connects to register.Because the databus will be an 8一bit bus, there are 8-bit Flip-flopsthat form the register, When there is information onthe data bus,and a particular register is selected toreceive data, all the Flip-flops will store data simultancously. This kind of register is refer is referred to as aparallel register.

例如，如果寄存器被联接到一台8位机的数据总线上，那么，该总线的每一条线均联接到寄存器上，因为数据总线是8位总线，所以有9个触发器来形成寄存器，当在数据总线上有信息，并且选择了一个特定的寄存器来接收数据时，那么所有的触发器将同时存储数据，这种形式的寄存器叫做&并行寄存器&。

Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package

M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装

Taking the communication server as the core,the data transmission layer collects data from other intelligent devices with 103 protocols,Modbus protocols,pro-bus protocols or TCP / Modbus protocols,which are converted as dual Ethernet network data and then transmitted to monitoring system and dispatch center via hub.

重点介绍了通信网络的构成，网络管理层基于TCP/IP的以太网络通信，采用站内103通信规约，数据传输层以通信服务器为核心，向下采集其他智能设备数据，支持任何采用103规约及采用Modbus通信规约、pro-bus通信规约或采用TCP/Modbus协议的智能设备，并将采集到的数据转换成以太网双网数据，通过交换机上传至监控系统及调度中心。

The absorption and distribution of chromium were studied in ryeusing nutrient culture technique and pot experiment.

采用不同浓度K2CrO4(0，0.4，0.8和1.2 mmol/L)的Hoagland营养液处理黑麦幼苗，测定铬在黑麦体内的亚细胞分布、铬化学形态及不同部位的积累。

By analyzing theory foundation of mathematical morphology in the digital image processing, researching morphology arithmetic of the binary Image, discussing two basic forms for the least structure element: dilation and erosion.

通过分析数学形态学在图像中的理论基础，研究二值图像的形态分析算法，探讨最小结构元素的两种基本形态：膨胀和腐蚀；分析了数学形态学复杂算法的基本原理，把数学形态学的部分并行处理理念引入到家实际应用中。