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combinational相关的网络例句

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State machine was made up of register of status and combinational logic circuit. The status can be transferred as presetting before according to control signal. It is the control center of adjust relative action of signal to finish special operation.

状态机由状态寄存器和组合逻辑电路构成,能够根据控制信号按照预先设定的状态进行状态转移,是协调相关信号动作,完成特定操作的控制中心。

Include:(1) Basic Principles,(2) Algorithmic Simplification Techniques,(3) Use modern design and development kits,(4) Combinational logic design,(5) Sequential Logic design.

课程内容包含:(1)基本原理,(2)简化逻辑技巧,(3)电脑辅助逻辑设计工具,(4)组合逻辑设计,(5)循序逻辑设计。

Conventional test generation algorithms for combinational logic circuits make use of backtracking during the search, that results in lowering down their running efficiency.

摘 要:传统的组合逻辑电路测试方法在搜索过程中都不可避免地要进行反向回溯,由于反向回溯的次数过多,往往会降低算法的效率。

MUX is a multi-input, single-output combinational logic circuit, in the algorithm used in the realization of circuits to address code in accordance with scheduling data.

详细说明:多路选择器是一个多输入,单输出的组合逻辑电路,在算法电路的实现中常用来根据地址码来调度数据。

To learn the principles of combinational and sequential logic circuits and to be familiar with the basis of digital system. The course will cover the contents of VHDL and the principles of CPLD/FPGA.

本课程之目标在於帮助学生了解数位系统中组合及序向逻辑的原理及设计方法,以建立数位系统设计之基础,并辅以VHDL硬体描述语言的模拟实习以验证理论并熟悉CPLD/FPGA之原理。

A model is proposed in this paper to deal with the signals which drive the combinational logic gates working at nonlinear region. The frequency analysis method is able to provide higher accuracy, while significantly speeding up simulations.

为了解决组合逻辑电路有时会工作在信号非线性区的问题,提出一种数学模型来精确描述瞬时错误在组合逻辑电路中传播过程。

Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of ClassicEPGlO chip of Altera Co. and the detailed analyses of typical examples are also given.

结合Altera公司ClassicEP610芯片的结构,研究了将演化算法应用于函数级数字组合逻辑电路的硬件演化,并且对典型实例进行了详细分析。

This design which is based on the WindowsXp platform, using Graphic editor and text editor of MAX+PLUS II, to design Linear block code through VHDL and Combinational logic. both of these realization are simulated.

本设计基于windows xp平台,采用MAX + Plus II软件中的图形编辑模块和文本编辑模块,运用VHDL对线性分组编码器的编码功能,进行组合逻辑电路设计以及VHDL设计,并对两种设计进行波形仿真。

By adding a single bit to a data register (212) of each of a plurality of TAP controllers (102, 106), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers.

通过向多个TAP控制器(102,106)的每一TAP控制器的数据寄存器(212)以及直接组合胶合逻辑添加单个位,能够访问所述多个TAP控制器,而无需额外的芯片管脚,并且无需额外的TAP控制器。

In this part, a frictional-electrical combinational experiment has been made and its result has been discussed.

本文还对摩擦静电相结合的方案进行了初步尝试,并分析讨论了试验结果。

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