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combinational相关的网络例句

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与 combinational 相关的网络例句 [注:此内容来源于网络,仅供参考]

Compared with Borda and Copeland method,because this method further distinguishes "good" and "poor" level,the conclusion of combinational evaluation is more accurate,the degree of division is better and it has very good consistency with the conclusion of each comprehensive evaluation method.

与Borda法和Copeland法相比,该方法通过进一步区分"优"和"劣"的程度,使组合评价结论更为精确,区分度更好,且与各综合评价方法的结论具有很好的一致性。

To improve the speed and efficiency of combinational logic circuit design, this paper presented a Game Genetic Algorithm.

为了有效提高组合逻辑电路进化设计的速度和效率,提出了一种基于博弈遗传算法的电路进化设计算法。

This paper presents a frequency analysis method to analyze the propagation procedure of transient error in combinational logic.

提出一种新颖的频率分析方法来计算瞬时错误在组合逻辑电路中的传播。

In the analysis of combinational logic circuit, should take into account gate delay time of the impact on the circuit.

在分析组合数字逻辑电路时,应该考虑门电路的延迟时间对电路产生的影响。

Introduction of digital circuit in the combinational logic circuit, individuals think quite good.

详细说明:介绍数字电路中的组合逻辑电路,个人认为挺不错的。

It is also configured for all 3 input logic and some logic between 4 and 7 input,and used for general combinational logic.

该单元还能实现全部 3输入逻辑和部分 4~ 7输入逻辑,也是一种满足通用逻辑应用的结构。

It is well known that any signal coming out of combinational logic is prone to glitch.

众所周知,任何出自组合逻辑的信号都容

A use of task and level-sensitive always block design compared the reorganization of the signal combinational logic example.

详细说明:一个利用task和电平敏感的always块设计比较后重组信号的组合逻辑的实例。

It is no storage, memory function, its output depends only on the input the same time, it is a combinational logic circuit.

它无存贮、记忆功能,其输出只取决于同一时刻的输入,因此属组合逻辑电路。

This method can be used to reduce power dissipation of combinational logic.

本文通过上述问题的研究,在设计流程的不同阶段解决自测试设计的测试功耗问题:在高层综合阶段,引入功耗约束和模块随机响应模型,自动生成低测试功耗、低面积开销的RTL电路结构;在逻辑综合阶段,针对测试功耗分别优化了电路结构和测试向量生成电路,以微小的故障覆盖率和面积开销为代价,最大程度降低测试功耗。

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