查询词典 clock frequency

A design and implementation method of the high speed modulation system, which adopted the new techniques of the FPGA and DAC based communication system,is presented in this paper. The effect of the key techniques of this system, such as the high speed digital signal processing for modulation, high speed based-band signal conversion, wide-band modulation, carrier suppression, high frequency and high precision system clock generation, is analyzed, and the solutions and performance analysis is also given. Finally, a high speed modulation system for space applications is implemented, can be used for high speed data transmission with QPSK, 8PSK, QAM or other kinds of digital modulation.

本论文依据正交调制原理，采用基于FPGA和DAC的设计技术，提出了一种高速、灵活的调制系统的设计方法，重点分析了系统组成的调制编码映射、基带脉冲信号转换、信号滤波、调制、系统时钟产生等关键技术环节的影响，解决了高速调制信号处理、高速数据转换、宽带调制、载波抑制、高频率高精度系统时钟的产生等关键技术问题，完成了一种适用于空间应用的高传输速率、多进制数字调制方式和调制体制灵活的数据传输调制系统的设计与实现，可在硬件设计不变的情况下，实现QPSK、8PSK和16QAM等多种调制方式的高速数据传输，QPSK调制速率达到500Mbps。

Based on the CMMB system signal model, symbol timing synchronization error, sampling clock offset error and carrier frequency offset error are analyzed carefully.

在建立CMMB系统信号模型基础上，分析了符号定时同步误差，采样钟偏移误差，载波频偏误差对CMMB系统性能的影响。

Also, by using a novel offset architecture, as opposed to completely overlapped architecture, for the differential transmission pair, a 33% reduction of thickness is achieved in the design of a miniaturized common-mode filter with multi-layer LTCC technology. In view of increasing need of high-speed clock and data circuits to control their skew problems, a design of LTCC delay line is then conducted. To improve the waveform distortion associated with the microstrip/stripline-type meander delay line, a miniaturized high-frequency 3-D delay line with grounded guard traces is introduced. By means of 3-D structure, the 233 ps delay time, which requires extra board space amounting to a factor of 2.34 by stripline type meander delay line, can be shrunk into an EIA 1206 form factor.

为因应高速时脉及高速线路的不断发展，用於控制讯号、时脉同步的延迟线路需求日益增加，接著讨论的题目便是应用低温共烧陶瓷制程技术设计多层的延迟线路元件，为了改善在微带线/带线型折线式延迟线路波形失真的问题，论文中提出以接地的防护线来设计小型化的三维多层延迟线路元件，比较应用带线型折线式延迟线路和应用三维架构设计的延迟线路元件，同样提供233 ps的延迟时间，多层架构设计之延迟线路可缩小至EIA 1206 的尺寸，省下2.34倍的电路板面积。

Tstab is equivalent to approximately 512 master clock cycles and depends on the programmed master oscillator frequency.

tstab相当于大约512个主时钟周期，并在程序主振荡器的频率而定。

The packet clock then goes into SOA to reduce the low-frequency amplitude noise and temporal fluctuation with the self-gain modulation effect of SOA.

利用半导体光放大器的自增益调制效应对组合滤波器提取的帧时钟进行整形，降低帧时钟的幅度噪声和时间抖动。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失