查询词典 clock frequency

Following the introduction of the basic principle of OFDM, some nonideal effects on the performance of OFDM systems are discussed, such as carrier frequency offset, symbol timing offset and sampling clock deviation.

本文在简要介绍了OFDM的基本原理、关键技术的基础上，针对同步问题进行了深入研究。首先分析了同步偏差中的频率偏差、符号定时偏差及采样时钟偏差对系统性能的影响。

This is done by the chain in the oscillator frequency plus or minus clock implementation.

这是通过在振荡器分频链上加、减时钟脉冲实现的。

You can specify a particular phase for the generated clock signal, and also a permissable tolerance (as some devices may be able to get near to, but not exactly, the frequency you require).

您可以定义生成的时钟信号的一个特地相位，或者一个可接受的误差范围（因为一些器件可能不能输出您需要的频率的精确值，只能输出接近的频率值）。

We compare the relative frequency differences of the two Crystal clock oscillators, and we get different results in different directions.

我们发现在不同方向上具有不同的结果，从而证明空间在不同方向上存在差异。

Via counting the input counter spot frequency clock pulse in the ultrasonic round-trip time,the measurement dis-tance is displayed.The algorithm is novel.

该数字式超声波测距仪对超声波从发射到返回的时间内输入到计数器特定频率的时钟脉冲进行计数，进而显示对应的测量距离。

At the last of chapter 7, a new improved measurement method using TIA is introduced high frequency clock signal.

在论文的最后一章中介绍了一个用于完成对jitter的性质进行时间间隔分析测试与验证的系统的设计。

This article introduced in detail does not have the electric cable to coordinate the controller the overall design and its hardware electric circuit, the software procedure: Voltage comparator, 2 frequency multipliers, synchronized clock electric circuit, 6 7SEDLED nixietube display circuit.

本文详细介绍了无电缆协调控制器的整体设计和其硬件电路软件程序其硬件电路组要有：电压比较器2倍频器同步时钟电路6位7SEDLED数码管显示电路系统软件包括：主程序子程序实现控制程序等实验表明：该无电缆协调控制器系统可以准确的对信号灯进行监控和教正，可以在一定程度上解决混合交通流的问题

We have researched the output characteristic of the SFRL in the condition of frequency detune, established its theoretical model, and demonstrated it with the experimental results (4) The application of the SFRL used in all-optical clock recovery is researched.

研究了当频率失谐时环腔的输出特性，建立了频率失谐时环腔的理论模型，并通过实验验证了该失谐理论。

The goal of this thesis is to use standard CMOS process to realize a 1.25Gb/s dual-loop data and clock recovery. To attain the aim of low power what we put emphasis on SOC, deep sub-micron CMOS technology is now being considered because of that advantages such as low power, highly integrated capacity. On the other hand, it does not require a frequency divider and we utilize demultiplexer to retime data.

本论文的主题在完成一个双回路的1.25Gb/s资料与时脉回复器，并且完全使用互补式金氧半制程来实现以达到低功率、高度整合的优点，为达到未来系统晶片强调的超低功率，我们更把时脉的频率降低且在不影响速度的前提下达到成效。

A7800 Features: 10 Mb s Manchester encoding decoding with receive clock recovery Patented digital phase locked loop decoder re- quires no precision external components Decodes Manchester data with up to g18 ns of jitter Loopback capability for diagnostics Externally selectable half or full step modes of opera- tion at transmit output Squelch circuits at the receive and collision inputs re- ject noise High voltage protection at transceiver interface (16V) TTL MOS compatible controller interface Connects directly to the transceiver cable A7800 Maximum Ratings: A7800 Pinout:· NPT IGBT technology · low saturation voltage · low switching losses · switching frequency up to 30 kHz · square RBSOA, no latch up · high short circuit capability · positive temperature coefficient for easy parallelling · MOS input, voltage controlled · ultra fast free wheeling diodes · solderable pins for PCB mounting · package with copper base plate

A7800特点： 10兆s曼彻斯特编码与接收时钟恢复专利解码数字锁相环解码器重新奎雷斯没有精确数据的外部元件曼彻斯特解码高达全部G18抖动纳秒环回功能用于诊断外部可选的一半或整步模式的歌剧和灰在传输和接收碰撞投入重新ject高噪音在收发器接口（16V的）马鞍山的TTL兼容控制器接口电压保护输出静噪电路直接连接到收发器的电缆 A7800最大额定值： A7800引脚说明：·不扩散核武器条约IGBT技术·低饱和电压·低开关损耗·开关频率可达30千赫·平方米RBSOA，没有锁定了高短路能力··正温度，便于parallelling·马鞍山消耗系数，电压控制·超高速免费·印刷电路板焊接的引脚安装·铜底板包续流二极管

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失