查询词典 clock frequency

At the maximum operating frequency, the clock duty cycle may vary from 40% to 60%.

在最高工作频率，时钟占空比可能会有所不同从40％至60％。

This is because the bandwidth required for a lot of time, CPU can only wait until the next clock cycle will be needed, because memory could not keep pace with CPU frequency.

这是由于当对带宽的需求很大的时候，CPU只能够等待下一个时钟周期才能够得到所需要的数据，因为内存的速度跟不上CPU的频率。

It not only records the number of input clock pulse, but also realize frequency, timing, producing beats, such as pulse and pulse sequence.

它不仅能记录输入时钟脉冲的个数，还可以实现分频、定时、产生节拍脉冲和脉冲序列等。

The Frequency registers are 28 bits; with a 50 MHz clock rate, resolution of 0.2 Hz can be achieved.

频率registersare28bits；有一个50兆赫的时钟速率，分辨率为0.2赫兹才能达到。

Then, on the basis of the functional verification, the system architectures of the radio frequency analog front end and the control logic circuit for the passive UHF RFID transponder are studied and designed with low-power design techniques. The RF AFE circuit includes rectifier, matching network, backscatter, regulator, AM demodulator, voltage reference, local oscillator and power on reset circuit, and so on. The control logic circuit contains clock synchronization module, decoding module, coding module, cyclic redundancy checksum module, power management unit, control unit, shift register and memory.

然后，在功能验证的基础上，重点研究了无源超高频射频识别标签芯片射频模拟前端电路和控制逻辑电路的系统架构，并采用低功耗设计技术对其进行了设计，射频模拟前端电路设计包括了整流器、匹配网络、反向散射电路、稳压器、AM解调器、电压参考源、本地振荡器以及上电复位电路等，控制逻辑电路设计包括了时钟同步模块、解码模块、编码模块、CRC校验模块、功率管理单元、控制单元、移位寄存器和存储器等。

The error signal is smoothed by loop filter, then it is used to change the control register of interpolator and decimator: The proposed algorithm can track the frequency shift of sampling clock. The algorithm is simulated in both AWGN and multipath fading channel.

这种方法在发送端相邻载波间采用差分QPSK调制，在接收端利用QPSK的差分解调信号获得同步误差信号，从而获得关于OFDM符号同步和采样钟同步调整的算法，其特点是无需专门的同步导频信号。

According to pulse oddment counting principle, a pulse signal counting circuit for differential ring lasers is designed based on XC3S400AN, a kind of FPGA chip with high performance. The structure of the circuit is described in VHDL language and realized through sequence control and synchronization process of high accuracy/frequency clock signal.

根据脉冲零头计数原理，应用高性能的FPGA芯片XC3S400AN，基于VHDL结构描述语言，对高精度高频率时钟信号进行时序控制及同步处理，设计出一种四频差动激光陀螺脉冲信号计数电路，并进行了实验测试。

By utilizing the cross gain modulation effect and the period 1 oscillation harmonic frequency locked in an optically injected semiconductor laser , we can extract the wavelength conversional individual channel optical clock from the optical time division multiplexing OTDM signal .

光注入半导体激光器会产生非线性单周期振荡特性，利用交叉增益调制效应及对单周期振荡的微波锁频效应，可从光时分复用信号中提取出波长转换的分路光时钟。

This is an ID card read the source code, only 8,052 on the clock read 125K frequency ID cards.

这是一个读取ID卡的源代码，仅依靠8052的时钟读取125K频率的ID卡。

The principle and composition of the passive hydrogen maser is introduced briefly,and an application of digital frequency modulation and digital servo to the passive hydrogen maser for improving the performance of the clock is expounded.The final test and analysis of the system are presented and the data indicate that the stability of the present system is much better than that of the original one.

简单介绍了被动型氢原子钟的组成及原理，阐述了基于数字调频和数字伺服的电子电路在被动型氢原子钟上的应用，并给出了设计的最终测试结果及其分析，数据表明该系统的稳定度比原有系统有很大提高。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失