查询词典 clock frequency

The Absolute frequency measurement is performed with the help of a femtosecond laser referenced to a commercial cesium atomic clock.

用一台以商用铯原子钟为基准的飞秒光频梳作为测量工具，对其频率进行了20次的精密测量，相对不确定度为5.0×10^(-14)。

To achieve a clock signal clk is the frequency of the function, you can look at the waveform simulation results.

实现一个将时钟信号clk 十分频的功能，可以通过波形仿真来看效果。

Then, you shouldnвt forget to increase the memory frequency devisor since the memory frequency is set up relative to the clock rate of the CPU.

然后，您shouldn в吨忘记，以增加记忆体频率devisor由于内存频率是成立相对时钟速度的处理器。

The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.

一个例子是，通过FIFO缓冲器，将8位ADC连接到16位数据总线的微处理器（图1）。

A new tool that can test the clock base frequency error of energy measuring devices and provide GPS standard time to calibrate real-time clock was introduced in this paper.

介绍了一种用来测量电能计量装置的时钟基频误差，并提供GPS标准时间以校准其实时时钟的新型工具。

For eliminating clock synchronization error in orthogonal frequency division multiplexing systems, a clock synchronization method worked over multipath fading channels was proposed.

为消除时钟同步误差对正交频分复用系统的影响。提出了一种可工作在多径衰落信道下的时钟同步方法。

It analyzes the influence of the time-frequency properties of atom clock on time-keeping error by quantity, and estimates the error of related physical measure caused by the time-keeping properties of atom time-frequency criterion-time resolution.

定量分析了原子钟的时间频率特性产生的守时时差，估算了原子时频标准的守时时差对有关物理量测量所产生的影响。

A flexible buffer was placed between the over-sampler and DPLL.Not only was 10bits data recovery implemented,but also the frequency of sampling clock was reduced to 2.5 times of the data frequency.The phase verification for 10bit parallel data by DPLL increases the accuracy rate of judgment and improves the bit error rate.

通过在过采样电路和数字锁相环之间增加弹性缓冲电路，在实现10bit数据恢复的同时，使采样时钟频率减小为数据频率的2.5倍，DPLL同时对10bit并行的数据进行相位检测判断，提高了判断的正确率，使数据传输的误码率得到改善。

Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package

M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装

The new system calls can efficiently adjust the time and frequency of clock, and improve the precision of clock output signal. The new time server can satisfy more time requirements.

这些新的系统调用对钟的时间和频率修正更有效，精度更高，这样就提高了时钟服务器的精度，可以为用户提供较高精度的时间源，以便满足各种时间要求。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失