查询词典 clock frequency

According to the power model of atomic clock, a new model of atomic clock noize of time-frequency domain and it's algorithm is presented preliminary.

本文借鉴原子钟噪声的幂率谱模型，初步提出一种时-频域原子钟的噪声模型及相应的计算方法。

On a breadboard, it is easy to set the clock -- just move the input wires to drive higher-frequency signals into the minute-hand section of the clock.

在模拟板，它很容易把时钟拨——只是输入导线开车高频信号进入minute-hand节的时钟。

Design the key circuits to realize X processors low power strategy, which include the circuit used to stop clock, the circuit of the microcode engine unit, frequency-dividing circuit and clock driving unit.

设计了与X处理器功耗控制相关的关键电路，包括包括停止时钟电路、微码部件电路、时钟驱动模块、分频比电路等； 4。

The frequency divider with an inverting unit and a plurality of switch inverters in series makes the two inphase selectively turned on synchronously and turned off synchronously, thereby the frequency divider, with low phase noise, can tolerate a high frequency clock.

本发明提供的分频器，通过反相单元及串联的多个切换反相器的运作，使每一切换反相器的同相开关可以选择性地同步开启或同步关闭，以使得具有低相位噪声的分频器可处理高频时钟。

Based on the frequency characteristic of the impulse, electromagnetism interference problem of clock circuit is studied, putting forward basic ways and means for design on the electromagnetic compatibility of clock circuit.

在分析脉冲频谱特性的基础上，研究了时钟电路的电磁干扰问题，提出了时钟电路电磁兼容设计的基本方法。

According to the chicking equipment for volt-monitor need to build up a standard clock,in order to achieve the request that the instrument carry on time accurate checking to the volt-monitor,this text introduced principle of the oscular clock chip PCF8583 with I2C bus,put forward to make use of the DS32KHz to provide the high stable frequency signal for PCF8583, thus carried out the project of the standard clock, and the interface design of PCF8583 with MCS51 is presented.

根据电压监测仪校验装置需要建立一个标准时钟，对电压监测统计仪进行时间精度校正的要求，介绍了I2C总线接口时钟芯片PCF8583的基本原理，提出了利用DS32KHz给PCF8583提供高稳定度频率信号，从而实现了标准时钟的方案，并给出了PCF8583与MCS51单片机接口设计。

7 To 3.3 V operating supply voltage 44.1 kHz sampling frequency 16.9344 MHz (384fs) system clock Built-in crystal oscillator circuit 16-bit, MSB rst, rear-packed serial data input format ( 64 fs bit clock) 8-times oversampling digital lter · 32 dB stopband attenuation ·+0.05 to -0.05 dB passband ripple Deemphasis lter operation · 36 dB stopband attenuation ·-0.09 to +0.23 dB deviation from ideal deem- phasis lter characteristics Attenuator · 7-bit attenuator (128 steps) set by microcontrol- ler Soft mute function set by parallel setting ·(approximately 1024/fs total muting time) Mono setting · Left or right channel mono selectable by micro- controller Built-in innity-zero detection circuit , two-channel D/A converter · 3rd-order noise shaper · 32fs oversampling Built-in 3rd-order post-converter low-pass lters 24-pin VSOP package Molybdenum-gate CMOS process

2.7至3.3 V工作电源电压为44.1千赫的采样频率16.9344兆赫（384fs）系统时钟内置晶体振荡器电路的16位，MSB在前，后包装的串行数据输入格式（64飞秒位时钟）8倍超采样数字滤波器·32分贝的阻带衰减·+0.05至-0.05分贝通带纹波去加重滤波器的运作·36 dB抑制频宽衰减·-0.09到0.23 dB的偏差认为不理想，症状困扰评估滤波特性衰减器·7位衰减器（128级）集由单片机在-莱尔软静音功能的平行设置·（共约1024/fs静音时间）单声道设置·左或右声道单声道微控制器可选的内置的无限零检测电路Δ，两通道的D / A转换器·第三阶噪声整形·32fs过采样内置三阶后转换器的低通滤波器24引脚VSOP封装钼栅CMOS工艺

A DPC ( 300 ) includes: a frequency source ( 310 ) for generating a clock signal; a delay line ( 320 ) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device ( 330 ) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices ( 500, 510, 520 ) and a combining network.

DPC(300)包括：频率源(310)，用于产生时钟信号；延迟线(320)，用于接收时钟信号并在输出抽头产生相移时钟信号；数字控制器件(330)，用于产生控制信号；以及开窗口与选择电路，用于产生输出信号，包括：时序逻辑器件(500、510、520)和组合网络。

The method includes acquiring with the frequency meter the tested clock signal and measuring its frequency; sending the tested frequency value to the data acquisition and processing module for calculation and processing regularly; and processing the frequency data comprehensively in the data processing output module and displaying output figure and historical data.

所述的方法包括：首先，频率计采集待测时钟信号，并测试其频率值；然后，频率计定时将测试得到的待测时钟信号的频率值发送给数据采集处理模块进行计算处理；最后，数据输出处理模块对接收数据采集处理模块处理后的频率数据进行综合处理，并将获取的图形数据和历史数据显示输出。

Clock master to be due to a certain frequency in order to work with the FLASH communication should * transmit clock signal, so if there is no clock signal, control will not work.

时钟，因主控要在一定频率下才能工作，跟FLASH通信也要*时钟信号进行传输，所以如果时钟信号没有，主控一定不会工作的。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失