查询词典 clock frequency

In a caesium clock, the optimum frequency corresponds to 9,192,631,770 oscillations of the microwave per second (just over 9 GHz in frequency), so dividing the output electronically by this number provides one-second 'ticks' of the atomic clock.

对于铯原子钟，其最佳频率是微波每秒振动9，192，631，770次(频率略高于9 GHz)，而用电路把输出的信号除以这个数字就提供了原子钟的一声"滴答"。

Below us Divider VHDL description of the source code for the completion of the clock signal CLK frequency of 2 hours, 4 frequency, frequency of 8 hours, 16 minutes frequency.

下面我们介绍分频器的 VHDL 描述，在源代码中完成对时钟信号 CLK 的 2 分频， 4 分频， 8 分频， 16 分频。

By utilizing the cross-gain modulation effect and the period-one oscillation harmonic frequency-locked in an optically injected semiconductor laser, we can extract the wavelength conversional individual channel optical clock from the optical-time-division-multiplexing signal. In a FP-LD, we numerically simulate the extraction of 20 GHz optical clock at 1550 nm from the 2×20 Gb/s OTDM signal at 1555 nm, and experimentally obtain the -105 dBc/Hz phase noise frequency division clock of 12.36 GHz to 6.18 GHz with simultaneous wavelength conversion from 1550.24 nm to 1545.91 nm.

采用一个FP半导体激光器作为全光分路时钟提取及波长转换器，数值模拟实现了从波长为1555 nm、速率为2×20 Gb/s的光时分复用信号中提取出波长转换为1550 nm、重复频率为20 GHz的分路光时钟，实验完成了从波长为1550.24 nm、重复频率为12.36 GHz光脉冲信号中提取出相位噪声为-105 dBc/Hz的波长为1545.91 nm、重复频率6.18 GHz的分频光时钟。

A CPU over-frequency method and system is composed of CPU, set module with BIOS ROM and CMOS RAM, control module of peripheral unit, storage module and time clock generation module. CPU over-frquency processing is completed automatically by executing CPU over-frequency program stored in BIOS ROM, meanwhile the highest FSB frequency value of CPU is obtained, and the system and peripheral unit can run at it. A testing for system stability is added to process of CPU over-frequency processing in order to ensure that the FSB frequency is applicable to the operation of CPU and peripheral unit.

一种CPU超频方法以及系统，包括CPU、具BIOS ROM及CMOSRAM的设定模块、外围装置控制模块、存贮器模块以及时钟产生模块组成，经过执行储存于BIOS ROM中的CPU超频程序后，自动完成CPU超频处理，并取得可供系统与外围装置稳定运作的最高的CPU的FSB频率值，于CPU超频处理的过程中，自动加入系统稳定性的测试，确保该FSB频率值适用于CPU与外围装置运作，使系统运作在超频状态下，亦能稳定地工作。

The clock frequency and reset threshold voltage are factory trimmed to spe- cific values.

时钟频率和复位阈值电压是工厂微调，固相萃取- cific值。

12MHZ clock frequency of microcontroller used by a switch input, Trigger Timing counts.

详细说明：采用12MHZ时钟频率的单片机，通过一个开关输入，触发定时计数。

In this thesis, an all-digital phase-locked loop with large multiplication factor is presented. This circuit can be applied to the video system as a clock generator. It receives the horizontal synchronous signal from the graphics card and then generates a high frequency pixel clock according to the monitor resolution setting to acquire the video signal data. The stability of this sampling clock affects the display image quality directly. If the pixel clock is not stable, the display image will be glittering or jittering.

在本论文中，我们提出一个高频率倍数的全数位式锁相回路，此电路可应用於视讯系统中的时脉产生器，其主要功能是接收显示卡发出的水平同步讯号，并依据使用者设定的萤幕解析度，产生高频像素时脉来撷取视讯讯号资料，取样点的稳定度直接影响到显示画面的品质，若是像素时脉不稳定，则显示画面会闪烁或抖动。

When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of propagation delay time (tDO 80 ns), data input setup time (tSU 40 ns), SCK high time (tHI 40 ns), and SCK rise and fall times of 5 ns.

当使用菊花链配置中的设备，最大时钟频率是由一个传播延迟时间（TDO的80纳秒），数据输入建立时间（台联40纳秒）的组合，SCK的时候（硫40纳秒），和SCK上升和下降5 ns的时间。

Just like their predecessors on the 90nm core, the new Pentium D processors feature a locked clock frequency multiplier.

就像他们的前辈的90nm核心的新奔腾四处理器专题锁定时钟倍频。

According to some estimation, to May the chip r600 must master clock frequency not below 800 MHz.

根据一些估计，可能必须掌握晶片R600时钟频率不低于800兆赫。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失