查询词典 clock cycle

In the fourth chapter, firstly it introduces the Boolean functions algebraic expressions of the 2-value clock-controlled stop-and-go generator and Gunther generator. It reveals the balanced property of the two kinds of Boolean functions, and studies the Walsh cycle spectrum and the autocorrelation function. It also obtains the coincidence rate of their output sequences with affine sum of some bits of input sequences, and analyzes their ability of resisting the best affine approximation cryptanalysis and differential cryptanalysis. Secondly, we properly present a new definition of the Best Affine Approximation, namely BAA on the Boolean vector functions, followed by the spectral characteristic of such defined BAA attacks through using the decomposition formula of the union distribution for random variables. A lower bound of such BAA attacks is proposed. Finally, we also study the spectral characteristic of the second kind of nonlinearity of Boolean vector functions, followed by a higher bound of such nonlinearity. Furthermore, the limited relationship between the second kind of nonlinearity of Boolean vector functions and the linear structure of the linear combination of every component is analyzed.

在第四章中，首先给出了2值密钥流"停走生成器"和"衮特生成器"中实际存在的布尔函数的代数表示，揭示了这两类布尔函数的平衡性，随后研究了它们的Walsh循环谱和自相关函数等，得到了它们的输出序列与输入序列中的某些bit的仿射项的符合率，分析了它们抵抗最佳仿射逼近攻击和差分攻击的能力；其次，我们合理地给出了布尔向量函数最佳仿射逼近的新定义，利用布尔随机变量联合分布的分解式考察了相应的谱特征，并给出了布尔向量函数与其最佳仿射逼近的符合率的一个下界；最后，我们还考察了布尔向量函数第二类非线性度的谱特征，给出了布尔向量函数第二类非线性度的一个上界，并揭示了布尔向量函数第二类非线性度与其各个分量的线性和的线性结构之间存在的制约关系。

A flexible form of register is connected to a free-running clock and has a 'clock enable' control input so that control logic can decide on a cycle-by-cycle basis whether or not to update the register's contents.

一种灵活的寄存器连接着自主运行的时钟，并有一个时钟使能控制输入端。用控制逻辑可以根据每个周期的需要来确定是否更新寄存器的内容。

The output sequence of i Mealy circuits s one clock cycle earlier than Moore circuits'.

前者比后者的输出序列超前一个时钟周期。

CPU clock speeds are measured in megahertz, or MHz, with each cycle known as a "clock tick."

CPU时钟速度单位是兆赫兹，或者是MHz，也就是每一周被称为"时钟周期"。

Can execute 2-3 simple instructions per clock cycle in one vertex pipeline.

PU在单条顶点流水线中，每个时钟周期能够执行2－3条简单指令

High-performance RISC CPU · Only 35 single-word instructions to learn - All single-cycle instructions except for program branches which are two-cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle · Interrupt capability (up to 7 internal/external interrupt sources)· 8-level deep hardware stack · Direct, Indirect and Relative Addressing modes

高性能的RISC CPU·只有35单条指令学习-除了程序分支是两个周期·工作速度：直流- 20 MHz的时钟输入DC - 200 ns的所有单周期指令指令周期·中断能力（/外部中断源，高达7内部）·8级深硬件堆栈·直接，间接和相对寻址方式

The master generates a ninth clock cycle and during this period the receiver pulls the SDA line LOW to acknowledge that it successfully received the eight bits of data.

主人产生了第九时钟周期，在此期间接收器拉SDA线低到承认，它成功接收数据的8位。

Also have an Index register: 6 bits that can be set by software, and a Random register: 6 bit register decremented every clock cycle. Constrained not to point to first 8 entries.

另外更有Index寄存器：他有6位能够由软件配置，和Random寄存器：一个6位的每个时钟周期都很递减的寄存器，并且不会小于8。

Also have an Index register: 6 bits that can be set by software, and a Random register: 6 bit register decremented every clock cycle. Constrained not to point to first 8 entries.

另外还有Index寄存器：它有6位可以由软件设置，和Random寄存器：一个6位的每个时钟周期都很递减的寄存器，并且不会小于8。

Also have an Index register: 6 bits that can be set by software, and a Random register: 6 bit register decremented every clock cycle. Constrained not to point to first 8 entries.

另外更有Index寄存器：他有6位能由软件设置，和Random寄存器：一个6位的每个时钟周期都非常递减的寄存器，并且不会小于8。

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失