查询词典 clock cycle

An externally controlled address bus selects one of the 108 filters in each clock cycle.

外部控制的地址总线选择在每个时钟周期的108过滤器之一。

At the end of the clock cycle it removes the address from the address bus and deasserts the READ signal.

在这个时钟周期结束时，微处理器撤消地址总线上的地址，并撤消读信号。

The SAA instruction on a Blackfin processor is fast because it utilizes four 8-bit ALUs in each clock cycle.

一个 Blackfin 处理器的 SAA 指令执行速度很快，因为它在每个时钟周期中可利用4个8bit ALU 。

In the first step, the CPU fetches the instruction byte from memory. To do this, it copies the value of the ip register to the address bus and reads the byte at that address. This will take one clock cycle.

第一步里，CPU从内存取得字节指令，为了做这些，它拷贝IP的值到地址总线并读取在那个地址的字节，这将花费一个时钟周期。

In the future, improvements will hopefully made so that several memory references will be made per clock cycle.

在未来的时间里，每个时周期完成几个存储器访问的技术相信是可以实现的。

During the first clock cycle, we need to actually load the instruction.

在第一个时钟周期，将装入指令到微处理器中。

This occurs when more than one Low-High transition takes place in a clock cycle over multiple cycles.

这发生在一个以上的由低到高的过渡发生在一个时钟周期的多个周期的地方。

1 Sequence of the system clock,One clock cycle later,to allow time for memory

一个时钟周期（允许存储器对地址译码和访问数据的时间）之后

Because each clock cycle has both a high and a low state, after the first clock pulse, two LEDs will always be on—that is, LED 1, LED 1 and 2, LED 2 and 3, LED 3 and 4, and so on.

因为每个时钟周期都是高低电平状态，第一个时钟脉冲后，两个LED通常是亮的——也就是说，LED1，LED1和2，LED2和3，LED3和4，等等。

Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package

M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装

By using competitive adsorption of activated carbom to remove unfavorable influence of carbon in carbonaceous gold concentrate on leaching process, the leaching rate of gold concentrate can be improved to 88% as compared with 10%by direct cyanidation.

本文论述了利用活性炭竞争吸附作用，消除含炭金精矿中炭在浸出过程中的影响，使金精矿的浸出率可由直接氰化的10％提高到88％。

The only thing you're ever gonna be king of is King of the Stupids!

你只配做傻瓜的国王！