查询词典 circuit

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Sample and hold circuit is an indispensable important circuit block, which almost determines the performance of the whole A/D converter.

采样保持电路作为模数转换器的必不可少的关键单元，很大程度上决定了ADC的性能。

In sample and hold circuit and Multiplying DAC, a gain-boosting op amp was used to insure the speed and precision of the Switch-capacitor circuit.

在比较器设计时，采用了前置放大器加动态锁存器的结构，达到了较快的速度，并减小了回程脉冲效应。

Sample and Hold Circuit The sample and hold circuit is used to take a narrow-band measurement of a time-changing signal and to hold that measured value until reset.

采样保持电路采样保持电路，是用一个窄波段测量时间变化的信号，并认为测值，直至复位。

In the system, a finepositioning window signal generating circuit redundant, sample and hold circuit of positioning error signal using no traditional charge/discharge method but high-speed switches and operational amplifier integrators, and cross-zero detector with threshold for higher reliability, is originated by the author in this paper.

综合面伺服和扇区伺服的各自优点，设计完成了4000 TPI光刻伺服解调系统：在设计中，首创了带冗余的精定位窗口信号生成电路，采用高速模拟开关和运放积分电路代替传统的电容充放电法，以完成精定位位置误差信号的平均与采样保持，使用带阈值的过零检测电路提高过道脉冲的可靠性。

To reduce the area of the layout,we use one-stage OP-AMP in the ROIC,and the sample and hold circuit shared by pixels in a column is also applied instead of sample and hold circuit in every pixel.

本设计采用电容反馈互阻抗放大器结构作为输入级，列共用方式的采样保持电路，源级跟随器作为输出级，用移位寄存器来控制行、列选通并控制电路工作的时序。

In formal we adopt 1.5-bit/per stage technology and a 2-bit flash ADC in the last stage. We adopt switch-capacitor circuit to design the sample and hold circuit and the multiplying DAC.

本次设计为九阶段的管线式类比数位转换器，前八个阶段采用1.5-bit/per stage的技术，最后一个阶段则为一个2-bit的快闪式类比数位转换器。

Considering the speed , power dissipation and specifications, A flip-around sample and hold circuit was designed to reduce the power consumption; S/H circuit is followed by eight 1.5-bit stages and a final 2-bit flash sub-ADC.

该流水线式ADC的采样保持电路采用Flip-around结构以减少功耗；前8级每级1.5位，最后一级为2位的并行flash ADC，并采用数字校正技术对级电路的误差进行校正，最终以达到10位的精度；为了达到系统低功耗的要求，该流水线ADC采用了运放共享技术和逐级缩小技术。

The ADC is pipelined, including a single-input/difference-output sample/hold circuit and nine stage subcircuits. The preceding eight stages are 1.5bits/stage, and the last stage consists of two comparators. Every input sample is converted into 18 bits binary signals, and these binary signals are converted into 10 bits binary signals through digital correction circuit.

模数转换电路采用流水线式的结构，包括具有单端输入/差动输出功能的采样保持电路和九级的子电路，前八级子电路使用1.5位/级的结构，最后一级使用两个比较器实现，每个输入值被转换为18位的二进制代码，通过数字纠正技术最终实现10位的输出，按照前端电路的应用要求，这个模数转换器实现1.33MHz的采样速率。

Circuit noise within the system: such as CRT deflection circuit power to the secondary emission of noise _ mother _ Sina fashion blog, fashion, mom, wedding photography network to provide in accordance with the relationship between noise and signal, image noise can be divided into additive and multiplicative noise two types of noise ...

系统内部电路噪声：如CRT的偏转电路二次发射电予的噪_时尚妈妈_新浪博客，时尚妈妈，婚纱摄影网提供按照噪声和信号之间的关系，图像噪声可分为加性噪声和乘性噪声两大类。。。

This one mode pays close attention to network credence foundation of the businessman very much.

这一模式非常关注商人的网络信用基础。

Cell morphology of bacterial ghost of Pasteurella multocida was observed by scanning electron microscopy and inactivation ratio was estimated by CFU analysi.

扫描电镜观察多杀性巴氏杆菌细菌幽灵和菌落形成单位评价遗传灭活率。