查询词典 cache

The work in this thesis is part of a Preliminary Research Projects. Based on the design of 32-bit embedded microprocessor "Longtium R2", designed and implemented the Dual-port Data Cache, which is applied to the "Longtium R2" microprocessor, achieved synchronization snooping, and effectively improved the processors performance. Based on the Dual-port RAM, studied Multi-port Data Cache, proposed a Sixteen-ported Data Cache.

本论文研究内容来自西北工业大学航空微电子中心所承担的某预研课题，以参与的32位嵌入式微处理器"龙腾R2"的设计工作为基础，设计并实现了基于双端口RAM的数据Cache，该Cache应用于"龙腾R2"微处理器，能够实现数据同步侦听，提高多机环境下处理器的性能；并在双端口RAM基础上，对多端口数据Cache进行研究，提出一个16端口数据Cache的实现方案。

In order to reduce the conflict of L1P in CMT,we propose the policy of logic partition L1P Cache by n power of 2 and the competing loop lock.Now the fairness researchs always need single thread sample phase,we propose a novel fairness policy:FROCM,it doesn\'t need single thread sample phase.We propose ring cooperant L1 data Cache,which can reduce both the complexity of the design and the load of L2 Cache.We also propose a method to exchange threads dynamicly based on fast-shared data pool,it can detect the data consanguinity of two threads in real time and exchange them into one core rapidly.At last,we design and implement a dual-core and dual-thread VLIW prototype YHFT DSP/DS based on the above studies.In order to enhance the bandwidth of data path and reduce the delay of critical path delay of CMT processor,we design a 10R/6W register file full customly.

为了减小多线程运行时指令Cache的冲突，本文提出了二幂等分指令Cache策略和循环锁竞争机制；现有对CMT处理器公平性的研究常常需要中断其它线程进行单线程采样，针对这个问题本文提出了多线程公平性策略FROCM；本文提出了环形协同数据Cache结构，以解决CMT处理器中共享存储体负载重，冲突大的问题；本文还提出了基于快速共享数据缓冲池的线程动态交换技术；最后本文实现了一个双核同时多线程芯片原型YHFT DSP/DS。

CPU cache size is also one of the important indicators, but also the structure of the cache on the CPU speed and size of the impact of very large, CPU cache in the operating frequency is extremely high and the processor is generally the same frequency of operation, efficiency is much larger than system memory and hard disk.

缓存大小也是CPU的重要指标之一，而且缓存的结构和大小对CPU速度的影响非常大，CPU内缓存的运行频率极高，一般是和处理器同频运作，工作效率远远大于系统内存和硬盘。

First, we analyse the associativity\'s impact on cache performance and energy consumption and discuss the way concatenation cache architecture.

主要研究内容包括：量化分析相联度对Cache性能和功耗的影响，并详细讨论路串联结构的工作原理。

CACHE there are three kinds of image and the way advantages and disadvantages and Cache memory in a few practical issues

还有CACHE的3种映像方式及优缺点和Cache存储器实用中的几个问题

You can look at the db cfg parms that make this:buffer pools, lock list,package cache, catalog cache and util_heap and check the sum of all these values.

即使是在 32 位世界中拥有十分干净的内存模型的 Solaris 上，用于 DB2 缓冲池的内存也不能超过 3.35 GB；4 GB 内存空间的其余内存必须专用于 DB2 的其它共享内存用途。

In this paper, a CMP cache design (tradeoff cache between latency and capacity, TCLC) is proposed.

提出了一种适用于CMP的cache结构－延迟和容量权衡的cache结构。

At first we test and verify the communality between original design and data acquisition system with FIFO cache; then we quantitatively analyze the performance of data acquisition system with FIFO cache, and the results are satisfied.

在数据采集系统的改进设计和实现中：首先对加入FIFO缓存后数据采集系统工作的一致性进行了验证；然后对加入缓存后系统的工作性能进行了定量分析得到了较为理想的结果。

The cache has a limited size, so not all the data on disk can fit in the cache.

由于数据缓存区的容量受系统的限制，因此磁盘内的数据不可能全部存入缓存中。

Try to do this in time – that would be impossible to do exactly, there are different factors that can affect the time, like file system cache, disk cache, distribution of files on a disk, what else is going on your computer, etc. The accurate estimation of time is possible only for processes which have speed and acceleration as natural characteristics.

尝试这样做的时间-这是不可能做到准确，有不同的因素会影响时间等文件系统缓存，磁盘缓存，磁盘上的文件分配，又是什么将您的计算机上，等时间的准确的估计可能只有进程具有速度和加速度的自然特色。

More direct, directer ; most direct, directest

径直的，笔直的

Do you know how to use a chain saw?

你知道如何使用链锯吗？