查询词典 cache memory

The boundary of analytical model and statistical model is clearly divided in this performance model, and evaluation accuracy is improved. Secondly, based on embedded SRAM performance hybrid model, this article adopts bionics algorithm-ant algorithm to optimize hierarchical embedded SRAM structure. This method which adjusts memory system structure improves memory system performance. Finally, considering the factors such as memory cell area, power, delay and reliability, this article establishes static 6-T memory cell area, power, delay and static noise margin equations, analyzes 6-T memory cell device dimension constraints under "read upset" and "write upset", then proposes a method to enhance embedded SRAM performance by optimizing 6-T memory cell size. In order to realize embedded SRAM design and verify proposed optimization methods, this article takes the Garfield202 system chip as the platform, which embeds A720T processor and 20KB Scratch-Pad memory.

首先针对嵌入式SRAM结构，采用多元线性回归方法分析SRAM宏单元性能指标，采用解析方法分析控制电路延时，结合以上这两种方法建立嵌入式SRAM性能混合模型，该模型清晰划分两种建模方法的各自适用范围，提高了模型精度；其次以该混合模型为基础建立存储体性能目标函数，采用仿生优化算法—蚂蚁算法优化嵌入式SRAM结构，使之达到最优设计；最后综合考虑面积、功耗、速度以及可靠性等因素，建立静态6-T存储单元面积、功耗、延时以及静态噪声容限方程，分析了&读破坏&和&写破坏&的晶体管尺寸约束，优化了6-T存储单元尺寸，提高了嵌入式SRAM性能。

This defines the path to cache directory, cache directory name, type and size of the cache area.

定义了到缓存目录的路径、缓存名称、类型以及缓存区域的大小。

Large-capacity hard disk cache can read and write in the work of state, so that more data is stored in the cache to improve disk access speed, but does not mean that the bigger the cache the more outstanding.

大容量的缓存虽然可以在硬盘进行读写工作状态下，让更多的数据存储在缓存中，以提高硬盘的访问速度，但并不意味着缓存越大就越出众。

Studied the expansion of the Dual-port Data Cache, designed a Sixteen-ported Data Cache, The simulation results showed that on the average, access time is decreased 20% over Single-port RAM based Data Cache.

对双端口数据Cache进行扩展研究，设计了一个16端口数据Cache，与单端口实现的16端口数据Cache相比，数据Cache平均访问时间降低了20％左右，且硬件实现相对简单，占用芯片面积少。

The work in this thesis is part of a Preliminary Research Projects. Based on the design of 32-bit embedded microprocessor "Longtium R2", designed and implemented the Dual-port Data Cache, which is applied to the "Longtium R2" microprocessor, achieved synchronization snooping, and effectively improved the processors performance. Based on the Dual-port RAM, studied Multi-port Data Cache, proposed a Sixteen-ported Data Cache.

本论文研究内容来自西北工业大学航空微电子中心所承担的某预研课题，以参与的32位嵌入式微处理器"龙腾R2"的设计工作为基础，设计并实现了基于双端口RAM的数据Cache，该Cache应用于"龙腾R2"微处理器，能够实现数据同步侦听，提高多机环境下处理器的性能；并在双端口RAM基础上，对多端口数据Cache进行研究，提出一个16端口数据Cache的实现方案。

In order to reduce the conflict of L1P in CMT,we propose the policy of logic partition L1P Cache by n power of 2 and the competing loop lock.Now the fairness researchs always need single thread sample phase,we propose a novel fairness policy:FROCM,it doesn\'t need single thread sample phase.We propose ring cooperant L1 data Cache,which can reduce both the complexity of the design and the load of L2 Cache.We also propose a method to exchange threads dynamicly based on fast-shared data pool,it can detect the data consanguinity of two threads in real time and exchange them into one core rapidly.At last,we design and implement a dual-core and dual-thread VLIW prototype YHFT DSP/DS based on the above studies.In order to enhance the bandwidth of data path and reduce the delay of critical path delay of CMT processor,we design a 10R/6W register file full customly.

为了减小多线程运行时指令Cache的冲突，本文提出了二幂等分指令Cache策略和循环锁竞争机制；现有对CMT处理器公平性的研究常常需要中断其它线程进行单线程采样，针对这个问题本文提出了多线程公平性策略FROCM；本文提出了环形协同数据Cache结构，以解决CMT处理器中共享存储体负载重，冲突大的问题；本文还提出了基于快速共享数据缓冲池的线程动态交换技术；最后本文实现了一个双核同时多线程芯片原型YHFT DSP/DS。

To address this feasibility problem, the nonvolatile memory was used as the main memory and part of the RAM as the cache, and a modified verification algorithm with cache policy was proposed. The analysis proved that this algorithm features strong transportability and feasibility.

采用非易失性存储器作为主存， RAM中的一部分空间作为缓存器，并且给出一种相应的Cache调度策略算法，尝试实现一种在卡上的Java卡的字节码校验算法，并且证明了该算法具有较好的可移植性和实现性。

We describe and compare five options for virtual address translation in the context of Distributed SharedMemory multiprocessors, including CC-NUMAs (Cache-Coherent Non-Uniform Memory Access Architectures) and COMAs (Cache Only Memory Access Architectures).

我们记录并对比了分布式共享内存多处理器环境下，包括CC-NUMAS(一致性高速缓存非均匀存储访问模型)和 COMA高速缓冲内存器存取模式）中的5个虚拟地址转换项目。

Dual Inline Memory Module HYS72V32300GR-7.5-C2, provides a 64-bit data path, and this type of interface to the memory of flapper contacts on both sides of the data interface, this interface model is widely used in the present computer memory , the usually 84-pin, because it is bilateral, so a total of 84 × 2 = 168 line contact, so people often called the 168 line to the memory of this memory, it is known as the 168 line memory.

双列直插式存储模块HYS72V32300GR-7.5-C2，提供了64位的数据通道，而且这种类型接口内存的插板两边都有数据接口触片，这种接口模式的内存广泛应用于现在的计算机中，通常为84针，由于是双边的，所以共有84×2=168线接触，所以人们常把这种内存称为168线内存，故称为168线内存条。

Study On Attention Resource Effect Of Event-based Prospective Memory Abstract Prospective memory refers to the memory of what will happen in the future. The conception of prospective memory exceeded the scope of memory's definition by traditional psychology, and extended the field of memory research.

基于事件前瞻记忆任务中的注意资源效应前瞻记忆是指对将来发生事件的记忆，包括基于事件的前瞻记忆、基于时间的前瞻记忆和基于活动的前瞻记忆三种基本的形式。

The shaping method of noncircular part and the tool holder's radial motion characters in noncircular turning process are discussed in detail in the thesis.

论文详细研究了非圆零件的成型方法和加工过程中刀架的径向运动规律。

I have not really liked him,I do not like his this kind of disposition.

我没有真的喜欢他，我不喜欢他的这种性格。