查询词典 bus master

First according to the character of LIN,the design scheme of the bus architecture is determined. Then, the circuit design of the bus nodes, including the master node and the slave node are discussed.

首先根据LIN总线的特点，确定了总线主机节点和从机节点的硬件结构和芯片选型，然后根据LIN总线物理层规范和通讯协议试验的需要，设计了一个具有三层结构的通讯试验平台。

And you generally _never_ want to use the physical address, because you can't use that from the CPU (the CPU only uses translated virtual addresses), and you can't use it from the bus master.

实际上你从来不需要使用物理地址，因为你不能在CPU上使用这个地址（CPU只使用映射后的虚拟地址）你也不能在外设上面使用这样的地址。

A mechanism for ensuring that a bus master does not extend the access latency of other masters beyond a specified value.

确保总线主控设备不把对其他主控设备访问等待时间扩展到指定值以上的机制。

I2C can be used to replace standard parallel bus to connect the various functional modules and integrated circuits. I2C is a multi-master bus, so any device can be the same as the master and control bus.

I2C能用于替代标准的并行总线，能连接的各种集成电路和功能模块。I2C是多主控总线，所以任何一个设备都能像主控器一样工作，并控制总线。

Data transfer operations are protected by CRC codes; therefore, any bit changes induced by card insertion and removal can be detected by the SD bus master.

数据传送操作是通过 CRC 编码来保护的，因此，由拔插卡引起的任何位的变动将会被 SD 总线管理器侦测到。

The key element in an embedded vector delivery strategy is the inclusion of an embedded oundary-scan controller, or JTAG test bus master.

关键因素嵌入式载体交付战略列入一个嵌入式oundary扫描控制器，或的JTAG测试总线主控。

SAK-C167CR-LM easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave BUSY and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 3.3V (0.3V) power supply Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP Industrial temperature range (-40C to +85C) is available for selected speeds

朔C167CR - LM滚动轻松扩展数据总线的宽度为32位或更多的使用主/从选择当级联多个器件M / S的=关于硕士M / S的=忙输出标志VIH VIL数值就投入繁忙和忙碌的奴隶中断标志片全部港口的仲裁逻辑芯片上的信号灯的信号港口之间的异步操作完全由硬件支持任何港口的LVTTL兼容，（为0.3V）电源可在84引脚PGA的，84引脚PLCC和单3.3V 100引脚TQFP工业温度范围（- 40C至+85 C）是选定的速度可

MBRD1035CTLT4G easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave BUSY and Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port LVTTL-compatible, single 3.3V (0.3V) power supply Available in 84-pin PGA, 84-pin PLCC and 100-pin TQFP Industrial temperature range (-40C to +85C) is available for selected speeds

1第1页，本页显示记录1-11，共11条记录分1页显示MBRD1035CTLT4G轻松扩展数据总线的宽度为32位或更多的使用主/从选择当级联多个器件M / S的= VIH对奴隶繁忙投入繁忙和中断标志对主M / S的= VIL数值忙输出标志上港口全部仲裁逻辑芯片的片上信号信号港口之间的异步操作完全由硬件支持任何港口的LVTTL兼容，（为0.3V）电源可在84引脚PGA巡回赛，84引脚PLCC和100引脚TQFP封装3.3V单工业温度范围（- 40C至+85 C）是选定的速度可

After powering, it firstly initializes I/O port, timer T0, UART and EINT, then tests whether someone puts down key; if there is, it runs corresponding ISR, the slave applies for bus control and sends its address to the master, then the master takes corresponding process.

电源接通后，先对LPC932的I/O口，定时器T0，串口和外部中断初始化，然后判断是否有按键，如有，则执行相应的中断服务函数，从机向总线申请控制权，发送从机的地址给主机，主机再进行相应的处理。

And then I send out a vagary suddenly , the bus deciding to sit returns to a master station, also can watch once more when going back, location sitting to depend on a window in master station, 8:00 penetrates time of north tetracylie presumedly much again.

心想，就这样走了挺遗憾的，我突发奇想，决定坐车回总站，回去的时候也能看到一次，然后在总站坐个靠窗户的位置，大概8：00多再穿回北四环，于是我做419到了总站，在那里突然发现另一路628也能绕行，就做了这个，还真是不错，628到了健翔桥大概8点，然后开始堵车，四环全是车人，主路车也开不动，车里的人全下来了，还有从辅路跳过护栏的人，这样，我可以在车里挺清楚的看见鸟巢，而且最好的是，在鸟巢正下方的时候赶上了一次放花哈哈

In the negative and interrogative forms, of course, this is identical to the non-emphatic forms.

。但是，在否定句或疑问句里，这种带有"do"的方法表达的效果却没有什么强调的意思。

Go down on one's knees;kneel down

屈膝跪下。。。下跪祈祷