查询词典 binary adder

A method for cold transportation of goods that are placed in a hollow-walled refrigerating container, comprising the following steps: storage of a pumpable solution of tiny ice crystals, known as binary ice, having a given composition and temperature, in a binary ice store until said binary ice is used for refrigerating or filling purposes; the optionally filled wall of the refrigerating container that is to be used is emptied via an outlet valve for the binary ice; binary ice is allowed to circulate inside the refrigerating container via filling instruments that are supplied with binary ice from the binary ice store until the temperature of the wall drops to a given temperature, whereby the heated fluid that is discharged from the outlet valve is fed to a binary ice fluid store; the wall of the refrigerating container is filled with a given amount of binary ice; the refrigerating container is decoupled from the filling instruments; the binary fluid that result from the melted binary ice is returned to a corresponding binary fluid store in order to produce new binary ice from said binary fluid.

一种置于一中空壁制冷容器里的制品的冷运输用的方法包括下列诸步骤：将一种具有一预定的组成和温度的可被泵送的小的冰晶体的溶液保存在一个二元冰储槽中，直到所述的二元冰用于制冷或充填目的；通过一二元冰出口阀将待被使用的一制冷容器的随意被充填的壁排空；用二元冰充入该制冷容器的被排空的壁内；通过充填器具使该二元冰在该制冷容器里循环，这循环由来自二元冰储槽的二元冰供给，直到壁温下降到一预定值，从而从该出口阀放出的被加热的流体被提供给一个二元冰流体储槽；将一给定量的二元冰充入该制冷容器的壁里；从诸充填器具上拆离该制冷容器；将从溶化的二元冰形成的二元流体返回到一相应的二元流体储槽内，以便从所述的二元流体制取新的二元冰。

This is my ISP programming experiment in the preparation of an independent structural description of the four full-adder, through the four mapping of a full adder means four full-adder function, together with a digital display module will be full adder computing the results output to a digital display.

详细说明：这是我在ISP编程实验中独立编写的采用结构化描述的四位全加器，通过四次映射一位全加器的方式实现了四位全加器的功能，并附有数码显示模块，将全加器的运算结果输出到数码管显示。

Make signal be called binary system numeral to make for the make of binary system signal, the binary system make and is divided into a binary system to move key to control(2 ASK), the binary system Pin move key to control(2 FSK), the binary system mutually move key to control(2 PSK) with bad cent the binary system mutually move key to control(2 DPSK) etc. variety basic type, this topic main is numeral the frequency make and call Pin to move key to control.

调制信号为二进制信号的调制称为二进制数字调制，二进制调制又分为二进制幅移键控（2ASK）、二进制频移键控（2FSK）、二进制相移键控（2PSK）和差分二进制相移键控（2DPSK）等多种基本的类型，本课题主要是数字频率调制又称频移键控。

The entire theory systems of the punctured binary sequence pair and the punctured binary array pair are built, which include the perfect punctured binary sequence pair theory, the perfect punctured binary array pair theory, the quasi-perfect and double quasi-perfect binary array pair theory, and the punctured binary complementary sequence pair theory.

定义了屏蔽二进序列偶、最佳屏蔽二进序列偶和奇周期最佳屏蔽二进序列偶，研究了它们的变换性质和存在的组合允许条件，并用这些性质和条件，搜索出若干最佳屏蔽二进序列偶和奇周期最佳屏蔽二进序列偶。

This is a 4-bit full adder, a half-price with a make a full-adder, and then made four half adder.

详细说明：这是一个4位全加器，用一个1位半价做的一位全加，然后做成的四位半加。

The relationships among perfect punctured binary array pair, quasi-perfect and double quasi-perfect punctured binary array pair is presented. Specially, when first and second dimension period of the punctured binary array pair are odd, the perfect punctured binary array pair, quasi-perfect and double quasi-perfect punctured binary array are able to change each other.

定义了准最佳屏蔽二进阵列偶和双准最佳屏蔽二进阵列偶，研究了它们的变换性质和频谱特性，给出了它们存在的组合允许条件，利用这些组合允许条件，有效地搜索出若干准最佳屏蔽二进阵列偶和双准最佳屏蔽二进阵列偶。

This procedure is to use two four parallel binary adder cascade manner through an 8-bit adder.

详细说明：本程序是利用两个4位二进制并行加法器通过级联方式构成一个8位加法器。

It is the hybrid of binary carry look-ahead adder of Brent-Kung~ and the carry select adder.

它结合了Brent-Kung对数超前进位加法器和进位选择加法器的优点，使得加法器的面积和连线减少了50%，而延时与加法器的长度的对数成正比。

Adder can be used to express a variety of values, such as: BCD, plus three yards, the major is based on a binary adder for computing.

加法器可以用来表示各种数值，如：BCD、加三码，主要的加法器是以二进制作运算。

Experiments on multiplier tree and adder tree expressions exhibit running time reduction of 83% to 99%, and 40% to 80% respectively.4. Arithmetic unit check with half adder graph technique: Binary Moment Diagram technique has been used in multiplier equivalence checking.

比如针对加法和乘法连续运算的表达式，算法从实现电路中提取变量顺序和结合顺序并加以利用，实验表明，在验证乘法连续运算的表达式时减少了83%～99%的时间，加法连续运算表达式的验证时间也可减少40%～89%。4。

Finally, the Knight strung a line between two of the monoliths and tied the horses up there.

最后，骑士们在两颗巨石之间拉了一条绳子，将他们的座骑绑在上面。

T7zN/hyS0 The island lies south by east from here.

那个岛位于此地的正南偏东方向。