查询词典 associative array processor

A processor which consists of following two subsystems: an associative array processor subsystem and a serial processor subsystem, which share the same main storage.

一种由以下两个子系统组成的处理机：一个相联阵列处理机子系统和一个串行处理机

In chapter two, this paper has made and explained operation course, the definition of the security investment fund and net value computing technology of the security investment fund at first; this paper uses time the analytical method of the array to analyse the array of net value of the fund, divide which into secular trend array , season index array , circulation fluctuate index array and random fluctuate index array and analyse them respectively.

在第二章，本文首先对证券投资基金的运作过程、证券投资基金的定义及净值的计算方法作了阐述，随后本文运用时间序列分析方法对基金净值序列进行分析，将其分解为长期趋势序列、季节指数序列、循环波动指数序列和随机波动指数序列并分别对其进行分析。

The array chip takes a flexible transparent polyimide thin membrane as the base, the lower surface can form a cross comb-shaped array multimicroelectrode, the electrode group is composed of two comb-shaped microelectrode array electrodes which are mutually crossed but not contacted with the electrical structures not being connected, and the microchannel between the both internal electrodes of the electrode group serves as the service passage; the array chip is inversely buckled on the fusion pool, and the cross comb-shaped array multimicroelectrode on the array chip correspondes to the cell electric fusion pool and falls in the cell electric fusion pool.

阵列芯片以柔性透明聚酰亚胺薄膜为基底，下表面通过蚀刻形成交叉梳状阵列化微电极组，电极组由两个相互交叉、互不接触、电气结构上互不连接的梳状微电极阵列电极构成，电极组内部微电极之间的微通道为工作通道；阵列芯片倒扣于融合池上，其上的交叉梳状阵列化微电极组与细胞电融合池相对应，落于细胞电融合池中。

The co-channel interference rejection filter for outputting a second input signal by removing co-channel interference from a first input signal; a first post processor for removing interference other than co-channel interference from the second input signal; a second post processor for removing interference other than co-channel interference from the first input signal; and a selection controller for selecting the output of the post processor which has less error by comparing the output of the first post processor with the output of the second post processor.

一种共道干扰消除器及其方法，其中抗共道干扰滤波器从第一输入信号中除去共道干扰并输出第二输入信号，第一后置处理器除去第二输入信号中的非共道干扰，第二后置处理器除去第一输入信号中的非共道干扰，选择控制器比较第一后置处理器和第二后置处理器的输出，从中选择误差较小的后置处理器输出。

Based on BAP array processor controller, we put forward a concept of embedded SIMD control core, which is the combination of RISC processor core used in multimedia and BAP array processor controller core. The embedded SIMD control chip can be flexibly customized using SIMD control core.

在BAP阵列处理器控制器的基础上，本文将针对多媒体应用的RISC处理器核与BAP阵列处理器控制器核进行结合，提出了一种嵌入式SIMD控制核的概念，利用SIMD控制核，可以灵活定制满足要求的嵌入式SIMD控制芯片。

First, based on phased array antenna's mono-pulse goniometry and separate coordinate technology about phase control, the antenna beam pointing error formula, caused by phase quantization error, is derived from linear array and circular array to planar array and cylindrical array.

首先以单脉冲相控阵天线测角原理为基本理论出发点，利用相位控制的坐标分离技术，基于线阵、圆形阵等简单形式的相控阵天线，推导了平面阵、圆柱面阵等相控阵天线由相位量化误差引起的波束指向误差公式。

By time-varying filtering, we realize the signal selectivity and interference suppression, especially for the signals with time-varying power spectrum. It is shown herein that conventional eigenstructure based methods are lower dimensional special case of the time-frequency subspace fitting method. The closed-form array response estimation algorithms for blind source separation in wireless communication is also developed in the dissertation by exploiting the data structure of second-order statistics of the array output in the presence of multipath. The proposed method achieves array response estimation with little constraint on signal property and propagation environment such as scatters or angular spread. Moreover, the array utilized here can be of arbitrary geometry and even uncalibrated. Since the closed-form solution is obtained, no misconvergency may occur and large amount of computation can be saved. The equivalent feed model and corresponding optimization designation are proposed to realize the downlink multi-user selective transmission. By coherent and non-coherent superposition of the electromagnetical field, multiple beams can be formed using a single array, so that each co-channel user signal is transmitted in each beam and will not interfered with each other. The proposed system scheme implements the digital beamforming and the channel allocation in the base band, therefore is suitable for the utilization of the radio software technology. The feasibility and effectiveness of the proposed model are proved by the RF experiment.

在窄带条件下，GSC－SSF方法还可以提高阵列的虚拟孔径，从而提高估计的性能；可以证明，Cyclic DOA 和SC-SSF方法可看作该方法的特例或近似； 3、提出了二维GSC－SSF方法和宽带谱相关DOA矩阵方法，利用信号的循环平稳特性解决了宽带条件下二维 DOA 估计问题，并具有阵元数少、计算量较小的特点； 4、提出了时频子空间拟合和宽带时频DOA估计算法，将联合时频分析的理论和方法引入到阵列信号的空间谱估计研究中，利用时变滤波实现信号选择性测向和干扰抑制，特别适合于谱时变信号；可以证明传统特征结构法可看作是时频子空间拟合方法的特例； 5、提出了多用户环境下阵列响应的估计方法——CARE方法，该方法对信号结构和传播参数（主要是散射源分布与角度散布）的约束较少，适用于各种几何结构的阵列甚至未校准的阵列，能够直接得到阵列响应的闭式解，因此计算量小、稳健性好，不存在收敛问题； 6、提出了针对多用户下行选择性发送的阵列等效激励模型、优化设计方法及其系统实现方案，通过空间场的相干叠加与非相干叠加使得单一阵列能够形成多个波束，并保证各波束内的用户信号各不相同且相互干扰最小；其系统方案具有在基带实现数字波束成形、信道分配并便于软件无线电实现的特点，其有效性已得到外场实测数据的证实。

The relationships among perfect punctured binary array pair, quasi-perfect and double quasi-perfect punctured binary array pair is presented. Specially, when first and second dimension period of the punctured binary array pair are odd, the perfect punctured binary array pair, quasi-perfect and double quasi-perfect punctured binary array are able to change each other.

定义了准最佳屏蔽二进阵列偶和双准最佳屏蔽二进阵列偶，研究了它们的变换性质和频谱特性，给出了它们存在的组合允许条件，利用这些组合允许条件，有效地搜索出若干准最佳屏蔽二进阵列偶和双准最佳屏蔽二进阵列偶。

Based on a lot of experiment results, a conclusion is drawn: comparing with other factors, the performance of branch handling strategy is the key limits of processor to exploit the instruction level parallelism existed in nonscientific code, cache miss have severe effect on superscalar processor's performance when it runs scientific code. Second, in order to reduce the branch penalty and improve the performance of superscalar processor, a new branch handling strategy—a classification based hierarchical branch handling strategy, CHBHS is proposed. It first expands the traditional processor architecture to support multiple condition code, conditional execution and Mbranch instruction, as a result, compiler can reduce the number of static conditional branch when the code is generated. Then, CHBHS tries to use the best suitable mechanism to deal with different branch base on their different behavior. CHBHS can predict the target address of unconditional branch, subroutine call and conditional branch by buffering their target address in branch target buffer, a newly proposed high efficient return address stack is used to reduce the penalty of subroutine return instruction, a new Counter Register Stack is also proposed to reduce the penalty of loop-closing branch to zero, and dynamic branch predictor is incorporate with branch target buffer to predict the outcome of conditional branch.

基于上述结论，为了尽量消除转移指令对处理器开发指令级并行性能力的影响，进一步提高处理器性能，在详尽分析目前已存在的转移处理策略的特点与局限性的基础上，首次提出了一种新的转移处理策略即基于分类的层次转移处理策略CHBHS(Classification Based Hierarchical Branch Handling Strategy)，它首先通过扩展传统的体系结构，支持多条件码、条件式执行及多分支转移技术，以使编译程序在进行代码生成时可尽量少生成条件转移指令，从而减少静态条件转移指令的数目；其次，基于不同的转移指令的行为不同这一事实，提出了对不同的转移指令采用不同的机制进行处理的思想，即对无条件转移指令和函数调用指令以及条件转移指令的目标地址，采用转移目标缓冲器来预测，对于函数返回指令，采用所提出一种的高效返回地址栈来预测其目标地址，对于大多数循环控制转移指令，采用所提出的Counter Register Stack来将其所可能带来的损失减少为0，对于其他的条件转移指令采用动态预测机制来预测其方向。

Each user is a Field-bus control node.SCM MCS-51 is used as its main processor,and Neuron CMOS as its assistant processor.The two processors cooperate with each other.the main processor sam pling and controlling,and the assistant processor taking chang of communication.

把整个系统作为一个LON网络，每个住户作为LON网络的一个现场控制节点并以MCS-51单片为主处理器，Neuron芯片为从处理器两处理器协同工作；主处理器采样控制，从处理器负责通信。

The use of the web to spread fears that flicking the switch on the LHC could create a Black Hole that could swallow up the Earth particularly concerned him, he said.

他说，使用互联网散布恐慌说启动LHC会生成一个可能吞噬地球的黑洞的做法让他感到忧虑。

Not a single word have I written down.

我一个字也没有写下来。