查询词典 adder-wort

We also design a new XOR-XNOR, used in our full adder, which can generate full swing signal at the same time.

此设计是由一种新的XOR-XNOR电路所组成，其能够同时产生XOR以及XNOR的full-swing输出。

Based on the I-V characteristics of single-electron transistor and the concepts of CMOS digital integrated circuit design, a full adder which consists of 28 complementary SETs is proposed.

基于单电子晶体管的IV特性和CMOS数字电路的设计思想，提出了一种由28个互补型SET构成的全加器电路结构。

Modelsim的同行-Modelsim the procedures for the development of a platform for the development of VHDL language, achieving a simple full adder...

本程序以Modelsim为开发平台，采用VHDL为开发语言，实现了简单的全加器。

It is based on an one column full adder in function; there introduces the special carry chain in the parallel and the vertical directions in order to accord the flexible carry needed by the data channel, it can be confected into different working mode, and realizes the compound logic and the sequence logic.

它在功能上基于一位全加器；在水平和垂直方向中都加入了专用进位链以满足数据通路所需的灵活进位，可配制为不同的工作模式，分别实现组合逻辑和时序逻辑。

This is my ISP programming in an independent experiment using a structured, prepared as described in a seven-member voting machine, through a unique 3 times a full adder mapping method in order to achieve a vote of seven functions, with the network on any other A seven-member voting machine source code must not identical.

详细说明：这是我在ISP编程实验中独立编写的采用结构化描述的一个七人表决器，通过独特的3次映射一位全加器的方法从而实现七人表决器的功能，与网络上任何其他的七人表决器源码决无雷同。

Using the proposed method, some neuron MOS circuits realizing two-variable common functions and a full adder are designed, and the ratio of the coupling capacitance in each circuit can be calculated conveniently.

在此基础上设计了实现常用二变量逻辑函数的神经元MOS电路和全加器等电路。

Based on the transition propagation analysis of the basic unit of full adder, a kind of single input change BIST sequences is generated which has been designated to be more effective than multiple input change sequences when highly robust delay fault coverage is targeted in a series of previous theoretical and experimental results.

已有的理论和实践表明采用单跳变测试序列比多跳变序列具有更高的测试鲁棒性。

Programmable logic gate, I-bit nanopipeline full adder and 4×4 nanopipeline array multiplier based on RTD-CMOS circuits are presented in this paper.

文中对数字电路中比较典型的可编程逻辑门、全加器电路进行了设计与模拟，并在此基础上对4×4阵列纳米流水线乘法器进行了结构设计。

When the cell is configured for XOR XNOR MUX scheme,it can achieve the functions such as one bit full adder and base multiplier cell and so on for datapath application.

该单元采用功能增强的MUX结构，在配置为异或同或多路选择器结构时，只用一个单元的开销就可实现一位全加器、基本乘法单元等适于数据通路应用的功能。

Based on a new modified Wallace multiplier structure, named bi-forked Wallace multiplier structure, this paper presents the design of a highly re-configurable Multiplier for VLIW multimedia-processor. We found a reusable design method to extend multiplier with full adder array. The Structure can enable 32/16/8 bit operands, and has been optimized for speed and area.

在VLIW多媒体芯片的设计过程中，针对传统乘法器与加法器的不足，提出了一种新的分叉华莱氏树结构的乘法器模型，采用可重用的模块化设计思想，通过重用一位全加器阵列对乘法器进行扩展，处理器可以在一个乘法器单元内部同时支持多个32/16/8位的乘法运算，同时使乘法单元的速度和面积均得以优化。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。