查询词典 adder circuit

At the register level,as in Figure 1,it is seen that the system comprises a storage register A and an adder circuit.

在登记的水平，如图1项，可以看出，该系统包括一个存储寄存器A和一个加法器circuit。

Parallel adder is a digital circuit, which can be calculated the number of addition.

详细说明：并行加法器是一种数位电路，其可进行数字的加法计算。

A VHDL prepared by the full adder, digital circuit design of an EDA example, may not be special, but should be able to use what they are doing.

一个用VHDL语言编写的全加器，是数字电路EDA设计的一个例子，可能不太特别，但是应该可以用一下的。

We can use software to do most calculation but not use hardware. The most basic circuit doing calculation in the computer is binary adder. For example, we can use of addition to do subtracting, continuous adding to do multiplication, and continuous subtracting to do division.

在电脑的世界里，可以做任何数字系统且复杂的演算，但是大多数的演算都藉由软体来解决，而非用硬体直接进行各种演算，电脑的硬体或其他数位电路在做算术运算时，最基本的电路往往只有二进位加法器而已，至於减法可藉由补数的加法解决，乘法等於连续的加法，除法则是连续的减法，可见加法器在运算数位系统中的重要性。

A digital integrator reduces circuit area and power consumption by implementing a two-stage integration for a decimator with only one adder.

减小电路面积和功耗的数字积分器只用一个加法器为一个抽取器实现两级积分。

A VHDL prepared by the full adder, digital circuit design of an EDA example, may not be special, but should be able to use...

一个用VHDL语言编写的全加器，是数字电路EDA设计的一个例子，可能不太特别，但是应该可以用一下的。

Based on the I-V characteristics of single-electron transistor and the concepts of CMOS digital integrated circuit design, a full adder which consists of 28 complementary SETs is proposed.

基于单电子晶体管的IV特性和CMOS数字电路的设计思想，提出了一种由28个互补型SET构成的全加器电路结构。

Using the proposed method, some neuron MOS circuits realizing two-variable common functions and a full adder are designed, and the ratio of the coupling capacitance in each circuit can be calculated conveniently.

在此基础上设计了实现常用二变量逻辑函数的神经元MOS电路和全加器等电路。

The algorithm combines the recognition technique of different coding methods in multiplier, the extraction technique of half adder graph in addition circuit, and the recognition technique of half adder tree structure of partial product addition circuit. With the extracted information, the register transfer level synthesis engine can generate a gate netlist that is logically correct and structurally similar to the implementation.

该算法结合了乘法器的编码方式识别技术、加法电路的半加树提取技术和部分积加法电路的架构识别技术来提取乘法电路的实现结构，以此生成与实现电路结构相似且逻辑正确的网表。

Graph 1 capacitor C is right simplifying amplifier circuit undertake communicating going Ou; Detailed circuit use level of a few gain and an adder, subtracter class.

式中AD(1-4)分袂是放大器A1到A4的差动增益，ACM(1-4)分袂是这四个放大器的共模增益，AD5是放大器A5的差动增益，ACM5则是A5的共模增益。Δ是电路中电阻器R4的容限。

This one mode pays close attention to network credence foundation of the businessman very much.

这一模式非常关注商人的网络信用基础。

Cell morphology of bacterial ghost of Pasteurella multocida was observed by scanning electron microscopy and inactivation ratio was estimated by CFU analysi.

扫描电镜观察多杀性巴氏杆菌细菌幽灵和菌落形成单位评价遗传灭活率。