查询词典 V-engine

In this dissertation, the author introduces some key concepts such as VP-shells, features of Core Functional Categories and particularly those of the light verb v into the study, and makes a detailed study of causative uses of both English ergative verbs and Chinese adjectival verbs. It is proved there exists the light verb v in Chinese causative uses.

本文引入了最简理论方案中的几个关键概念，如VP 壳、核心功能语类，尤其是轻动词v 及其句法特征，并运用这些概念对英语作格动词的致使性用法和汉语使动用法进行了详细的分析，确定了汉语使动用法中轻动词的存在及其句法结构，并合理地解释了在轻动词的影响下语序的改变以及致使意义的产生过程。

The relationship between field of view and departure maneuver is developed.(2) The departure trajectory and safety characteristic are discussed for V-bar departure, R-bar departure and arbitrary direction departure.

1研究了视场约束下V-bar撤离的径向和切向冲量方案，利用解析和数值结合的方法得到了冲量大小和视场角的关系；(2)针对V-bar分离、R-bar分离和任意方向分离，分别研究了分离后的相对轨迹及被动安全特性。

Investigate, report, and resolve insulation resistance less than that stated by manufacturer's literature or less than allowable 25 megohms for equipment rated 250 V and less and 100 megohms for equipment rated more than 250 V.

调查报告，并解决绝缘电阻低于这个由制造商的文学作品所允许的25 megohms或多或少对设备达到250v及少、额定100 megohms设备额定250多V。

The 3d transition metal monoxides coordinate one noble gasatom in forming the linear NgMO(M=Cr, Mn, Fe, Co, Ni; Ng=Ar, Kr, Xe) complexes.(3) The group VB metal oxides MO_2 and MO_4 coordinate two and one noble gasatoms in forming the MO_2_2 and MO_4(M=V, Nb, Ta; Ng=Ar, Kr, Xe)complexes.

3第VB族金属二氧化物与两个稀有气体原子形成的MO_2_2(M=V，Nb，Ta；Ng=Ar，Kr，Xe)络合物，其四氧化物与一个稀有气体原子形成的MO_4(M=V，Nb，Ta；Ng=Ar，Kr，Xe)络合物。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

In terms of luminance performance of BLUs, there shows no much difference between V-cut and U-cut microstructures from simulation results. However, U-cut microstructure outperforms V-cut one in luminance uniformity.

另外在整体BLU辉度并未因入光侧添加微结构而有大幅的变化及差异的前提下，U-cut纵沟微结构的使用效果会比V-cut纵沟微结构来的好，除了在入光测量测点均齐度提升略胜一筹外，其入光侧明暗不均问题亦可处理地更为淡化，以达到光学及品味之最佳化。

Three control factors, involving in the optimization process: the pitch and depth of both V-cut and U-cut, and angle and radius for V-cut and U-cut, respectively, are the same as full factorial experiment method.

后同全因子实验选定入光侧V-cut纵沟微结构三组控制因子及入光侧U-cut纵沟微结构三组控制因子。

Simulation results of systems with V,v connection, three-phase-to-four-phase connection and single YN,dl 1-275 connection are showed in this paper. The proposed configurations of cophase AT power supply systems, balance compensation methods, comprehensive detecting reference currents are proved to be true and feasible.

针对本文给出的同相牵引供电系统，基于Matlab/Simulink建立了仿真模型，给出了V，y接线、三相变四相平衡接线和单台YN，d11-275接线的同相AT牵引供电系统仿真结果，仿真结果证实本文给出的同相AT供电系统结构

The sightline control strategy for bad measure precision is developed, and the control methods for vertical direction, approach direction and station keeping are presented.(2)The safe approach velocities are investigated for cuboid, sphere and cone keep out zone.(3)The design method for optimal trajectory under safety constraint is developed. The cone and cuboid keep out zone can be described using line constraint, and then optimal trajectory design can be translated to line programming problem under line constraint.(4) The design strategy of collision avoidance maneuver is discussed, and the collision avoidance scheme is analyzed for V-bar and R-bar approach.The control and trajectory safety in departure phase are investigated.

1提出了测量误差较大时平移靠拢段的视线控制策略，给出了横向、纵向和悬停的控制方法；(2)针对长方体禁区、球形禁区和锥形禁区三种禁区形式，研究了V-bar逼近和任意方向逼近的纵向安全速度计算问题；(3)提出了安全约束下的最优轨迹设计方法，将冲量和有限推力作用下的最优轨迹设计问题转化为线性规划问题，并给出了将锥形和方形安全区域约束转化为标准线性约束的公式；(4)探讨了紧急避撞机动的设计策略，分析了V-bar和R-bar接近的紧急避撞机动方案。

The split between the two groups can hardly be papered over.

这两个团体间的分歧难以掩饰。

This approach not only encourages a greater number of responses, but minimizes the likelihood of stale groupthink.

这种做法不仅鼓励了更多的反应，而且减少跟风的可能性。