查询词典 RISC

By utilizing EDA disign tool, C compiler of RISC soft-core processor and a number of FPGA resources, we can use or reuse IP to accomplish various experiments that the students are interested in, to train system design ability of the students.

通过使用EDA设计工具，RISC软核处理器的C编译器以及大量的FPGA资源，可以使用或者重复使用IP来完成各种学生感兴趣的实验项目，培养和锻炼学生的系统级设计能力。

Within RISC,teams of hardware engineers and complier architects work together to forge a unified design ne that will minimize the hardware complexity by integrating in hardware only such instructions that are justified by their occurrence in program trace analysis.

在RISC中，硬件工程师的编译设计师合作制定出一个统一的设计思想：即通过仅将那些由其在程序跟踪分析中的出现而正式的指令集成于硬件，从而将硬件的复杂程序降为最低。

High-performance RISC CPU · Only 35 single-word instructions to learn - All single-cycle instructions except for program branches which are two-cycle · Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle · Interrupt capability (up to 7 internal/external interrupt sources)· 8-level deep hardware stack · Direct, Indirect and Relative Addressing modes

高性能的RISC CPU·只有35单条指令学习-除了程序分支是两个周期·工作速度：直流- 20 MHz的时钟输入DC - 200 ns的所有单周期指令指令周期·中断能力（/外部中断源，高达7内部）·8级深硬件堆栈·直接，间接和相对寻址方式

FJ: Historically, the success of any computer architecture is due to a good match between the architecture and the implementation technology, as well an growing market for workstations that are powered by those architectures, eg, VAX architecture for DEC, RISC architecture for SUN and MIPS, do you envision such a great coincidence will happen again in computer industry in the coming decade?

福建：从历史上看，任何成功的计算机体系结构的原因是一个良好的比赛之间的架构和执行技术，以及一个不断扩大的市场工作站是由这些架构，例如疫苗架构12月的RISC描述了Sun和MIPS ，你设想这样一个伟大的巧合再次发生在计算机产业在未来十年？

Perhaps the most ironic part is that in some ways, macro-op and uop fusion are really making x86 MPUs interally more CISC-like, and less RISC-like.

也许具有讽刺意味的是，从某种程度上来看，它使得x86处理器更像是 CISC 处理器而不是 RISC 处理器。

The compiler prearranges the bundles so the VLIW chip can quickly execute the instructions in parallel, freeing the microprocessor from having to perform the complex and continual runtime analysis that superscalar RISC and CISC chips must do.

编译器预先安排好这种捆绑，因而VLIW能快速地平行处理指令，免去了微处理器不得不执行复杂和连续的运行时间分析，而超级标量RISC和CISC芯片必须做这种分析。

Most processors, including the IBM 370 family, the PDP-10, the Motorola microprocessor families, and most of the various RISC designs current in mid-1993, are big-endian.

采用这种机制的处理器有IBM3700系列、PDP-10、Mortolora微处理器系列和绝大多数的RISC处理器。

In 1989, we familiar to ear 80486 chipses be released by the INTEL, the great place of this kind of chip lies in the boundary that it broke 1,000,000 transistors actually, integrating 1,200,000 transistors.80486 clock frequencies raise a 33 MHzs, 50 MHzs gradually from the 25 MHzs.80486 is 80386 help processor with mathematics,80387 and 1 high speed of 8 KBses saves an integration slowly in a chip, and in the 80 X86 the serieses for the very first time adopted a RISC technique, can carry out an instruction in a clock period.

1989年，我们大家耳熟能详的80486芯片由INTEL推出，这种芯片的伟大之处就在于它实破了100万个晶体管的界限，集成了120万个晶体管。80486的时钟频率从25MHz逐步提高到33MHz、50MHz.80486是将80386和数学协处理器80387以及一个8KB的高速缓存集成在一个芯片内，并且在80X86系列中首次采用了RISC技术，可以在一个时钟周期内执行一条指令。

Nx586 processors be regarded as the "ethnic people", he has the performance can be more than the sun at high noon at the time of the Intel processors, and has a "half-human, half horse," features: it is the world's first to use a CISC structure and the structure of the mixed-RISC processor.

Nx586被看作是处理器领域的&人马族&，他所拥有的性能可以完全超过当时如日中天的Intel处理器，而且拥有着&半人半马&的特征：它是世界上第一款同时使用CISC结构和RISC结构的混合处理器。

Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package

M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸，那乌黑、忧郁的眼睛，她便会相信，他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失