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RISC相关的网络例句
与 RISC 相关的网络例句 [注:此内容来源于网络,仅供参考]

It was a descendant of the Stanford MIPS project led by John Hennessy, one of the three pioneering RISC research projects of the early 1980's.

它属于80年代早期的3个RISC研究项目之一,由约翰·亨耐希带领的斯坦福MIPS项目的后续产品。

Integrated 10BASE-T/100BASE-TX/1000BASE-T transceivers · 10/100/1000 tri-speed MAC · Host interfaces - PCI v2.2, 32/64-bit, 33/66-MHz - PCI-X v1.0, 64-bit, 133-MHz · MII/GMII/TBI interfaces for external transceivers · Ultra-deep, 96-KB on-chip packet buffer · Dual high-speed RISC cores with 16-KB caches - Programmable, in-line packet classification · SMBus controller · On-chip power circuit controller and Wake on LAN power switching circuit

集成号10Base-T/100Base-TX/1000Base-T收发器·10/100/1000三速陆委会·主机接口- 2.2版的PCI,32/64,33/66-MHz -的PCI - X的1.0版,64位,外部收发器133兆赫·信息产业部/的GMII / TBI的接口·超深,96 KB的片上分组缓冲·具有16 KB的缓存双高速的RISC核心-可编程,在线数据包分类·SMBus控制器·片上电源电路控制器和网络唤醒电源开关电路

A topdown design of an 8bit RISC MCU is presented, in order to overcome the limitation of MCS51 microcontroller The core is based on Harvard architecture with 16bit instruction length and 8bit data length The performance of the MCU has been greatly improved by introducing singleclockcycle instructions, setting multiple highspeed working registers, replacing microprogram with direct logic block, etc FPGA verification and computer simulation show that its maximum clock frequency and instruction e...

在对传统的MCS51系列单片微控制器的局限性进行分析的基础上,设计了一种基于增强8位RISC构架的微控制器内核。该MCU核采用哈佛结构、16位指令字长和8位数据字长,通过设计单周期指令、在内部设置多个快速寄存器及采用硬布线逻辑代替微程序控制的方法,加快了微处理器的速度,提高了指令的执行效率。计算机仿真验证和FPGA仿真验证的结果表明,该MCU的最高时钟频率和指令执行效率等指标均优于MCS51的5倍以上。

The design of the special-purpose 32-bit floating-point RISC chip is a major project of the National Defense Science and Industry Committee of China during the 9th 5-year-plan. This paper studies the design of the datapath in the chip, including low-power design techniques, the design of barrel shifter, adder, incrementer, fixedpoint and floating-point ALU, fixed-point and floating multiplier, and register bank.

本文以国防科工委"九五"期间重点课题专用32位浮点RISC为对象研究了该芯片的数据路径设计,其内容包括低功耗设计技术、桶式移位器、加法器与增值器、浮点算逻部件、定浮点乘法器、寄存器组等的设计等。

ABSTRACT TMS320C80 is one of the most powerful multimedia video processors in the world, which integrates a RISC main processor with standard floating point processing unit, four advance parallel DSPs, an intelligent transfer controller, and a video controller. It's capable of processing video in real-time.

TMS320C80是世界上功能最强的多媒体视频处理器之一,在单一芯片上集成了一个带标准浮点运算单元的RISC主处理器、四个高级的并行数字信号处理器、一个智能的传输控制器和一个视频控制器,具有强大的实时视频处理能力。

What is pipelining, anyway It helps RISC processors run more quickly, but how

它使RISC 型处理器运行的更快,那么是怎么实现的呢?

Based on the design of instruction pre-fetch FIFO for an embedded RISC processor, a SDRAM power model has been presented to optimizing the FIFO design.

本文从一个嵌入式RISC处理器的指令FIFO设计出发,提出了SDRAM的功耗模型,基于该功耗模型,提出了最优化的指令FIFO设计。

Of course, there is much more to HPC than RISC.

当然了,关于 HPC 的知识不只是 RISC 这方面的。

The design and the verification of SOC based on RISC MCU core were also discussed in this paper.

研究了片上系统的相关技术,并完成了基于RISC MCU核的片上系统的设计与验证。

And you'll still have the benefits of a powerful 32-bit RISC processor.

而您仍然有一个强大的32位RISC处理器的优势。

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推荐网络例句

As she looked at Warrington's manly face, and dark, melancholy eyes, she had settled in her mind that he must have been the victim of an unhappy attachment.

每逢看到沃林顿那刚毅的脸,那乌黑、忧郁的眼睛,她便会相信,他一定作过不幸的爱情的受害者。

Maybe they'll disappear into a pothole.

也许他们将在壶穴里消失

But because of its youthful corporate culture—most people are hustled out of the door in their mid-40s—it had no one to send.

但是因为该公司年轻的企业文化——大多数员工在40来岁的时候都被请出公司——一时间没有好的人选。