查询词典 RAM cache

According to one embodiment, a method of coherency management in a data processing system includes holding a cache line in an upper level cache memory in an exclusive ownership coherency state and thereafter removing the cache line from the upper level cache memory and transmitting a castout request for the cache line from the upper level cache memory to a lower level cache memory.

根据一个实施例，数据处理系统中一致性管理的方法包括：在处于独占所有权一致性状态的较高级别高速缓存存储器中保存高速缓存线，以及其后从较高级别高速缓存存储器移除高速缓存线，并且从较高级别高速缓存存储器发送对高速缓存线的掷出请求到较低级别高速缓存存储器。

First, the effects of magnetic RAM relaxation time and the rise-time of incident pulse signal on reflection signal are discussed, the relationship between the rise-time of incident pulse and relaxation time based on the energy of reflection signal is revealed. Then, the effects of magnetic hysteric, susceptibilities and saturation upon reflection signal are analyzed, the results reveal the reflection of RAM target and UWB signal design. In the meantime, dielectric relaxation time effect about dielectric RAM target is analyzed simply, and the effects of relaxation time and the width of incident pulse upon reflection signal are probed. Finally, a few RAM targets are measured in the chamber using the impulse radar experiment system which is developed by the team of anti-stealth impulse radar on Department of Electrical Engineering, National University of Defense Technology. The experimental results show the similarity of the rule of echos with the theory. From the compared results of different tagets, we concluded, compared with 15% wideband sinusoidal signal, the impulse signal has increased 10～12dB energy from the same loaded RAM target; this, in turn, shows the nonlinear effects of RAM to the echoes, and the potentiality of the impulse signal to RAM targets.

首先分析了磁性RAM的弛豫时间及入射脉冲信号的上升时间对反射信号的影响，从反射信号能量角度出发，给出了入射脉冲上升时间与弛豫时间的关系；接着分析了磁性RAM的磁滞特性、磁化率及磁化强度对反射信号的影响，给出了RAM目标辐射和有关UWB信号设计的一般性结论；其次，对介电RAM的弛豫时间效应作了简单的分析，探讨了介电弛豫时间及入射脉冲宽度对反射信号的影响；最后利用国防科技大学电子技术系&反隐身冲激雷达技术研究组&研制的冲激雷达实验系统，在微波暗室中对几种不同的RAM目标进行了测量，结果表明：其反射波形的基本规律与上述理论分析相一致；从各种不同目标回波的能量对比结果得出，涂覆RAM目标对冲激信号的吸收比15％带宽的正弦信号要小10～12dB，证实了RAM的非线性效应对回波的影响，也证实了冲激信号反隐身的潜力。

The first level cache is split caches : instruction cache and data cache, each of which is single-cycle cache with direct-mapped organization. The second level cache is a hybrid and multicycle cache with two-way skewed-associative organization.

NRS4000是一个32位的嵌入式RISC产品，时钟频率为20MHz，采用5级流水技术，实现了面向寄存器的指令集（共128条指令），支持了寄存器窗口切换和基于优先级的中断、故障、跟踪、通信等功能，是一个完整的微处理器系统。

The failure rate; that failure rate monitor is unit trends monitoring to apply below distinct Cache size with the process and the Cache that increase advantageous position differentiates algorithm expanded the Cache with conventional optimum failure rate differentiates algorithmic, numerary of Cheng of basis application line differs to give application to gift when undertaking Cache differentiates different power worth, the application that has more line Cheng in order to make obtains more sharing Cache, improve integral performance of the system thereby.

失效率监控器以进程为单位动态监控在不同的Cache容量下应用的失效率；而加权Cache划分算法扩展了传统的失效率最优的Cache划分算法，根据应用线程数目的不同在进行Cache划分时给应用赋予不同的权值，以使具有更多线程的应用获得更多的共享Cache，从而提高系统的整体性能。

There used to be two primary methods to optimize program data locality: the first is to analyze cache behavior of program data, then basing on cache behavior model, build a program analysis tool which shows the bottlenecks of data cache performance and hence directs programmer to tune performance of data cache; the second is program transformation by an optimizing compiler or an optimizing tool, and data cache performance is optimized in the transformation.

过去在这方面的工作有两个重要的思路：一是针对程序运行时的访问数据，利用相关的Cache行为模型，建立一些程序分析工具，从源代码级给出程序Cache性能的瓶颈，指导程序员通过程序变换来优化程序的局部性，从而提高Cache性能；二是在编译器上开发编译优化过程，或者开发专门的程序优化工具，通过对程序进行分析，在此基础上自动进行程序变换，包括代码变换和数据变换两种，优化程序的局部性，从而提高 Cache性能。

The characteristics of FIFO, double-port RAM and ping-pang cache structure were compared. The principle and features of ping-pang cache structure were discussed, and a real ping-pang cache structure was also given which consisted of high-speed, large capacity SRAM and FPGA. For a video processing system, this ping-pang cache structure is easy to interface with AD, DA and DSP.

文中比较了FIFO、双口RAM、乒乓缓存结构三种数据缓存电路的优缺点，讨论了乒乓缓冲控制器的结构和原理，并以高速、大容量的SRAM 以及FPGA器件为基础，设计了一种适应于高速DSP图像处理系统的乒乓缓存结构，其特点是速度快、所需器件少，易于与DSP器件接口。

By default attribute cache and directory entry cache are enabled, file data cache and file entry cache are disabled.

默认情况下，属性缓存及目录项缓存是开启的，而文件数据缓存和文件项输入缓存则是关闭的

Net reduction of fractions to a common denominator does not put server of a cache, the user visits cache server actually, server of again former website reads cache server take content, will read extraction content cache to arrive this locality.

网通分别放一个缓存服务器，用户实际访问缓存服务器，缓存服务器再原网站服务器读取内容，并将已经读取的内容缓存到本地。

Studied the expansion of the Dual-port Data Cache, designed a Sixteen-ported Data Cache, The simulation results showed that on the average, access time is decreased 20% over Single-port RAM based Data Cache.

对双端口数据Cache进行扩展研究，设计了一个16端口数据Cache，与单端口实现的16端口数据Cache相比，数据Cache平均访问时间降低了20％左右，且硬件实现相对简单，占用芯片面积少。

The work in this thesis is part of a Preliminary Research Projects. Based on the design of 32-bit embedded microprocessor "Longtium R2", designed and implemented the Dual-port Data Cache, which is applied to the "Longtium R2" microprocessor, achieved synchronization snooping, and effectively improved the processors performance. Based on the Dual-port RAM, studied Multi-port Data Cache, proposed a Sixteen-ported Data Cache.

本论文研究内容来自西北工业大学航空微电子中心所承担的某预研课题，以参与的32位嵌入式微处理器"龙腾R2"的设计工作为基础，设计并实现了基于双端口RAM的数据Cache，该Cache应用于"龙腾R2"微处理器，能够实现数据同步侦听，提高多机环境下处理器的性能；并在双端口RAM基础上，对多端口数据Cache进行研究，提出一个16端口数据Cache的实现方案。

In contrast to the ubiquitous rising-sun-with-rays military flag of the Japanese, Chinese banners and ensigns feature a range of designs.

与遍地都是的太阳军旗不同，中国人的旗帜和徽章设计得各式各样。

From their small corner of Feng's Guangzhou headquarters -- a jumble of pink leashes, squeezable rubber steaks, and plastic doggy Santas for Fido's stocking -- Soleil's designers come up with at least five new products a month.

从Feng 设在广州总部的产品展示柜台上可以看到，Soleil的设计师每月至少设计出5件新产品。