查询词典 NAND gate

Once we can build an inverter, building an AND gate is easy just invert the outputof a NAND gate.

一旦我们可以建立一个转换，建立一个AND是很简单的，只需要转换NAND的输出。

This program alone reduced prices on quad nand gate ICs from $1000/each to $3/each, permitting their use in commercial products.

这一计划降低价格仅基于NAND门电路四方1000/each元3/each元，允许他们在商业用途的产品。

Pulse width generator 404 delays the output signal VIN of NAND gate 403 to generate an output signal VOUT.

脉冲宽度发生器404延迟NAND门403的输出信号VIN从而生成输出信号VOUT。

Inverters 505 and 506 are coupled together in series between NAND gate 403 at VIN and a second input of multiplexer 510 to form a second delay path.

反相器505和506在NAND门403的VIN和乘法器510的第二输入端之间串联耦合到一起从而形成第二延迟路径。

Might be, pattern-based technology mapping was borrowed from software industry decades ago, now the problem is, IP, is not NAND gate, NOR gate, NOT gate any more, it itself is highly complicated hardware, difficult to be abstracted and modeled.

可能，模式化测绘技术是借来的，从软件业几十年前，现在的问题是，知识产权，是不是的nand门，也没有门，门没有任何更多的，它本身是极为复杂的硬件，难以被抽象和模仿。

Inverters 501-504 are coupled together in series between NAND gate 403 at VIN and a first input of multiplexer 510 to form a first delay path.

反相器501-504在NAND门403的VIN和乘法器510的第一输入端之间串联耦合到一起从而形成第一延迟路径。

After the UP and DN signals both become a logic high at the same time, NAND gate 403 generates a falling edge on VIN.

在UP和DN信号同时都变为逻辑高电平后，NAND门403产生VIN的下降沿。

After the UP and DN signals transition to a logic low, NAND gate 403 generates a rising edge in VIN, and pulse width generator 404 generates a rising edge in VOUT a delayed period of time later.

在UP和DN信号转换到逻辑低电平后，NAND门403在VIN中生成上升沿，且脉冲宽度发生器404在延迟时间段后在VOUT中生成上升沿。

NAND gate 403 is a logic gate that performs a NAND Boolean logic function on the UP and DN signals to generate a voltage signal VIN.

NAND门403是对UP和DN信号执行NAND布尔逻辑功能以生成电压信号VIN的逻辑门。

The time delay (T1) that NAND gate 403 takes to generate a falling edge in VIN plus the time delay (T2) that a falling edge in VIN takes to propagate through pulse width generator 404 to VOUT plus the time delay (T3) for flip-flops 401 and 402 to generate falling edges in the UP and DN signals after a falling edge in VOUT equal the minimum pulse width of the UP and DN signals (T1+T2+T3=MPW).

NAND门403在VIN中生成下降沿的时间延迟(T1)加上VIN中的下降沿通过脉冲宽度发生器404传递到VOUT的时间延迟(T2)再加上触发器401和402在VOUT中的下降沿后在UP和DN信号中生成下降沿的时间延迟(T3)等于UP和DN信号的最小脉冲宽度，即(T1+T2+T3=MPW)。

However, as the name（read－only memory）implies, CD disks cannot be written onorchanged in any way.

然而，正如其名字所指出的那样，CD盘不能写，也不能用任何方式改变其内容。

Galvanizes steel pallet is mainly export which suits standard packing of European Union, the North America. galvanizes steel pallet is suitable to heavy rack. Pallet surface can design plate type, corrugated and the gap form, satisfies the different requirements.

镀锌钢托盘多用于出口，替代木托盘，免薰蒸，符合欧盟、北美各国对出口货物包装材料的法令要求；喷涂钢托盘适用于重载上货架之用，托盘表面根据需要制作成平板状、波纹状及间隔形式，满足不同的使用要求。