查询词典 Memory

There is a close relationship between monoamines and learning and memory. NE and dopamine are believed to have a role in facilitation of memory. For this, an observation of clausenamide on monoamines and their metabolites as well as monoamine oxidase B activity was carried out.

目前认为脑内单胺类递质的变化与学习记忆密切相关，其中DA，NE的增加有助于学习记忆的形成，为了探讨黄皮酰胺的促智作用机制，我们首先研究了黄皮酰胺对小鼠脑内单胺类递质及其代谢产物和单胺氧化酶的影响。

See also Nozaki et al.,"A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application," IEEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar element in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory element channel to form a separate select transistor.

还参见Nozaki等人的&A1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application&(IEEE Journal of Solid-State Circuits，第26卷，第4期，1991年4月，497-501页)，其描述了处于分裂栅极配置中的类似元件，其中掺杂的多晶硅栅极在存储器元件沟道的一部分上延伸以形成单独的选择晶体管。

At very fast 100 us and low +/- 9 V P/E, good memory device integrity of 2.8 V initial memory window and large ten-year extrapolated retention of 1.8 V at 85oC or 1.5 V at 125oC are obtained in SiO2/Hf0.3N0.2O0.5/HfLaON/TaN MONOS device. Such excellent 85~125oC retention with small decay rate, at only 2.9 nm thin tunnel SiO2, is possible by tuning Hf0.3N0.2O0.5 trap energy deep into Si forbidden bandgap close to midgap.

在快速(100毫秒)和低电压(9伏)的操作条件之下，可得到2.8伏的记忆视窗；在85oC 和125oC环境下由外插法所得的十年资料储存能力，其记忆视窗仍有1.8伏和1.5伏，由於我们调整高含氮量氮氧化铪的捕陷能阶深入至靠近矽中间能带的禁止能带中，才能在仅2.9奈米穿遂氧化层的MONOS元件中，拥有如此突出的资料储存能力。

MAX1999EEI Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

MAX1999EEI引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S配对样本的支持下，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/遥测分比率为背景的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口的软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

TDA4864 Pinout: 8- to 32-bit and 16- to 32-bit word packing options Programmable wait state options: 2 to 31 CCLK Digital audio interface includes six serial ports, two pre- cision clock generators, an input data port, three programmable timers and a signal routing unit Serial ports provide: Six dual data line serial ports that operate at up to 50 Mbits/s for a 200 MHz core on each data line each has a clock, frame sync, and two data lines that can be configured as either a receiver or transmitter pair Left-justified sample pair and I2S support, programmable direction for up to 24 simultaneous receive or transmit channels using two I2S compatible stereo devices per serial port TDM support for telecommunications interfaces including 128 TDM channel support for telephony interfaces such as H.100/H.110 Up to 12 TDM stream support, each with 128 channels per frame Companding selection on a per channel basis in TDM mode Input data port provides an additional input path to the DSP core configurable as either eight channels of I2S or serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port Supports receive audio channel data in I2S, left-justified sample pair, or right-justified mode Signal routing unit provides configurable and flexible connections between all DAI components, six serial ports, an input data port, two precision clock generators, three timers, 10 interrupts, six flag inputs, six flag outputs, and 20 SRU I/O pins Serial peripheral interface Master or slave serial boot through SPI Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, and phases 3 Muxed Flag/IRQ lines 1 Muxed Flag/Timer expired line ROM based security features: JTAG access to memory permitted with a 64-bit key Protected memory regions that can be assigned to limit access under program control to sensitive code PLL has a wide variety of software and hardware multi- plier/divider ratios JTAG background telemetry for enhanced emulation features IEEE 1149.1 JTAG standard test access port and on-chip emulation Dual voltage: 3.3 V I/O, 1.2 V core Available in 136-ball BGA and 144-lead LQFP packages Lead free packages are also available

TDA4864引脚说明： 8 - 32位和16 - 32位字包装选择可编程等待状态的选择：2至31个CCLK数字音频接口包括6个串行端口，两个前643时钟发生器，输入数据端口， 3可编程定时器和一个信号路由单元串行端口提供：六双串口数据线，在高达50 Mbps的操作/为200兆赫的每个数据行每个人都有一个时钟，帧同步的核心秒，和两个数据可以作为任何一个接收器或发射器对左对齐和I2S样本对支持，最多可同时接收或传送24个频道，每使用两个系列的I2S兼容立体声设备配置可编程方向线；港口的TDM通信接口，包括支持128个电话接口的TDM的渠道，如H.100/H.110支持多达12个的TDM流的支持下，每帧128个频道每个压缩扩展每通道的基础上选择在TDM模式输入数据端口提供了一个额外的输入路径的DSP核心配置为I2S或串行数据或7加一个20位宽的SYN -异步的并行数据采集接口通道或8通道；支持接收通道I2S音频数据，左对齐样本对，或右对齐模式信号路由单元组件之间提供所有戴配置和灵活的连接，6个串行端口，一个输入数据端口，两个精密时钟发生器，3个定时器，10个中断，六旗投入，产出6个旗，20曼谷南南区域股的I / O管脚串行外设接口的硕士或奴隶通过SPI串行启动全双工运作主从模式多主机支持开漏输出可编程波特率，时钟极性和第三期合并调制旗/ IRQ线路1合并调制旗/定时器过期线光盘的防伪特征：JTAG的访问与64位受保护的关键允许内存内存可分配给程序访问控制的限制下对敏感地区有一个代码锁相环/分比率背景遥测的JTAG仿真功能增强的IEEE 1149.1 JTAG标准测试访问端口软件和硬件多钳各种各样和片上仿真双电压：3.3六/输出，可在1.2 V核心136球BGA封装和144引脚LQFP封装无铅封装，也可

Unlike the popular method of reconstructing public memory in contemporary art practice, this series of Wang Yins works has developed from personal experience and memory.

和当代艺术中那种重塑公共记忆的流行做法很不相同，王音的这一批作品大都是从个人经验和记忆入手。

Voice Memory, allowing players to pre-configure and store up to four different harmony voicings and step through them with the memory advance footswitch.

语音记忆，让球员预先配置和存储多达4种不同的和Xievoicings和步骤透过它们与记忆体预先脚踏开关。

Firstly it introduces relevant technical developments and trends, the task background and significance of the study, then analyzes hardware circuit of using image sensor as images collected, and utilizes the SAA7113 chip to deal with video image beforehand, SAA7113 lets the output of standard digital video signals to storage in FIFO memory, and decodes clock signals, Highlighted microprocessor control external circuit design of false coin and counting, and DSP control external circuit design, such as memory expand ect;Finally analyses CPLD as logic controller to control the logic and scheduling of some part ,and gives the undee emluator of some logic circuit.

文章首先阐述人民币智能分捡器相关技术的发展状况、发展趋势以及课题背景与研究意义；然后设计了利用图像传感器采集人民币图像输出模拟视频信号的硬件电路，以及利用视频解码芯片(SAA7113)对模拟视频图像进行预处理，SAA7113输出的标准数字视频信号存入FIFO存储器，同时还解码输出场、行同步信号、像素时钟信号送入CPLD等部分电路；重点设计了单片机控制验钞、点钞等外围电路，以及DSP控制的外围电路，如存储器的扩展等部分；最后完成CPLD对部分器件的逻辑和时序控制设计，并对逻辑电路的功能进行仿真，仿真结果令人满意。

The true beloveds of this world are in their lover's eyes: lilacs opening, ship lights, school bells, a landscape, remembered conversations, friends, a child's Sunday, lost voices, one's favorite suit, autumn and all seasons, memory, yes, it being the earth and water of existence, memory.

世界的可爱之处只活在那些爱她的人眼里：盛开的丁香，海船的灯光，学校的铃声，优美的风景，难忘的谈话，相知的朋友，童年的星期天，遗忘的说话声，最喜欢的一套衣服，秋天和其他季节，回忆——对，回忆，这是活下去的水和泥土。

The true beloveds of this world are in their lover's eyes: lilacs opening, ship lights, school bells, a landscape, remembered conversations, friends, a child's Sunday, lost voices, one's favorite suit, autumn and all seasons, memory, yes, it being the earth and water of existence, memory.

7楼世界的可爱之处只活在那些爱她的人眼里：盛开的丁香，海船的灯光，学校的铃声，优美的风景，难忘的谈话，相知的朋友，童年的星期天，遗忘的说话声，最喜欢的一套衣服，秋天和其他季节，回忆——对，回忆，这是活下去的水和泥土。

He paid $5,000 for this cupcake.

他我这个纸杯蛋糕花了5000美元。

I mean, if you want to, that is

我的意思是，如果你们想吃的话。