查询词典 FIFO

a kind of design project of multifunction electric power quality gauged instrument based on virtual instrument is put forward in this article.this system integrates virtual instrument programming and power electronics together,to realize diverse signals of current electric power quality field allin one.the integrated signal generator unit which carries out the collection of high speed digital data,d/ a conversion and analog output in four channels,unsymmetrical synchro control fifo etc.by fpga are introduced,the flow of electric power system various signal which generates by vc programming is elaborated,and the structural design of signal amplification unit is analysed.the experiment text result shows that this gauged instrument has attained current advanced high grade of accuracy and it will accelerate the steps of electric power quality calibration because of its accuracy and versatility.

摘 要：提出一种基于虚拟仪器技术的多功能电能质量标定仪的设计方案，采用虚拟仪器编程技术和电力电子技术相结合实现集目前电能质量领域的多样信号于一体。介绍采用fpga实现高速数字量采集、d/a转换及4通道模拟量输出、非对称同步控制fifo等的集成信号发生单元，阐述利用vc编程实现的电力系统多样信号的产生流程，分析信号放大单元的结构设计。实验测试结果表明该标定仪达到目前先进的高精度等级，由于其准确性和多功能性将加快电能质量标定的步伐。

AFA and AFC indicate when the FIFO contains more than a selected number of words.

发与亚足联表明何时比1的FIFO包含选定的数目字。

This is the design of better asynchronous FIFO a reference, I hope can be useful to everyone.

详细说明：这是设计异步FIFO的比较好的一个参考资料，希望可以对大家有用。

At first we test and verify the communality between original design and data acquisition system with FIFO cache; then we quantitatively analyze the performance of data acquisition system with FIFO cache, and the results are satisfied.

在数据采集系统的改进设计和实现中：首先对加入FIFO缓存后数据采集系统工作的一致性进行了验证；然后对加入缓存后系统的工作性能进行了定量分析得到了较为理想的结果。

Assume that we have to design a FIFO with following requirements and We want to calculate minumum FIFO depth

假充我们需要设计如下需求的FIFO，我们需要计算它的最小深度。

This paper presents synchronous FIFO integrated in FPGA which can achieve the function of high-speed buffer and bus synchronous data transmission by high-speed reading-writing operation of the FIFO.

本文提出一种基于FPGA片上集成的高速FIFO实现采集数据的高速缓存并通过对高速FIFO的读写操作实现总线同步数据传输，提高数据的传输速率。

Aiming at the high-speed matching controlling problems between adaptive filters inplemented by FPGA and the high-speed AD converters, a high-speed sampling and adaptive filtering system was designedusing asynchronous FIFO. The dual channels AD converter AD9238-40 was used as input stage, two asynchronous FIFOs on-chip were used as high-speed buffer memory, and the sampling and adaptive filtering was controlled by FPGA. The asynchronous FIFO was customized and simulated on Quartus II, the sampling and adaptive filtering controller was designed and also simulated on Quartus II. The high-speed matching controlling of the dual channels AD converter AD9238-40 and the adaptive filter was implemented.

针对用FPGA实现的高速自适应滤波器与高速ADC数据处理速度不匹配、容易产生串扰等问题，提出了一种基于异步FIFO技术的高速采样自适应滤波系统方案，选用双通道高速AD9238-40作为前置输入级，用片内异步FIFO作高速缓存，用FPGA控制采样与滤波，给出了系统的结构框图，对异步FIFO与采样滤波控制器进行了仿真，并将异步FIFO与采样滤波控制器集成在同一FPGA上，完成了对双通道高速AD9238与自适应滤波器的高速匹配控制。

The design scheme considers the circuit structure in transistor level by using the principle of adiabatic computing, which can effectively avoid the inevitable problems of metastability and asynchronism signals treatments in FIFO based on conventional complementary metal oxide semiconductor logic. A 16-depth adiabatic FIFO based on CTGAL was achieved.

该方案运用绝热计算原理，基于晶体管级设计电路，有效避免了传统CMOS逻辑的FIFO必然遇到的亚稳态和异步信号处理等难题，实现了深度为16的基于CTGAL电路的绝热FIFO结构。

Based on the design of instruction pre-fetch FIFO for an embedded RISC processor, a SDRAM power model has been presented to optimizing the FIFO design.

本文从一个嵌入式RISC处理器的指令FIFO设计出发，提出了SDRAM的功耗模型，基于该功耗模型，提出了最优化的指令FIFO设计。

The invention provides a dual redundant CAN bus controller, which is arranged on a crewel CAN bus, characterized in that: two CAN bus transceiving modules, two initializing modules are respectively corresponding to the CAN bus controller module A and CAN bus controller module B; the two CAN bus controller modules are respectively connected to the two CAN bus via a driver shifting control unit; the initializing module is connected to the bus control initializing register for initializing the e CAN bus controller modules; a protocol processing module is connected to the FIFO buffer; the FIFO buffer is connected to the node processor via the logical interface; a intermitting process unit sends the corresponding intermitting control signal to the CAN bus transceiving modules according to the CAN bus controller modules; one path of the CAN bus controller module is directly connected to the protocol processing module; another path is connected to the protocol processing module via the bus receiving buffer.

本发明提供了一种双冗余CAN总线控制器，设置于双线CAN总线上，其特征在于：两个CAN总线收发模块、两个初始化模块分别与CAN总线控制器模块A和CAN总线控制器模块B相对应；两个CAN总线控制器模块通过驱动器切换控制单元分别与两条CAN总线相连；初始化模块与总线控制器初始化寄存器相连，对所对应的CAN总线控制器模块进行初始化；协议处理模块与FIFO缓存器相连；FIFO缓存器通过逻辑接口与节点处理器连接；中断处理单元根据CAN总线控制器模块的控制命令对CAN总线收发模块发出相应的中断控制信号；CAN总线收发模块一路与协议处理模块直接相连，另一路通过总线接收缓存器与协议处理模块相连。

This one mode pays close attention to network credence foundation of the businessman very much.

这一模式非常关注商人的网络信用基础。

Cell morphology of bacterial ghost of Pasteurella multocida was observed by scanning electron microscopy and inactivation ratio was estimated by CFU analysi.

扫描电镜观察多杀性巴氏杆菌细菌幽灵和菌落形成单位评价遗传灭活率。