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CPU相关的网络例句
与 CPU 相关的网络例句 [注:此内容来源于网络,仅供参考]

All the main logic CPU/memory/control units are there (looks like 4 of them).

所有的主要逻辑CPU,存贮及控制部件都在这里,。

After gather related information in CPU registers, and then switch to the original core service program.

在对CPU寄存器进行相关的信息收集工作后退出再转入原内核服务程序。

Based on the above ideas, I will use line buffer as a first design. And then integrate loop buffer as my second design. Finally we use instruction content bus to deliver the buffer access position as my third design. Under this design, the buffer inside CPU core can store the nested loop and reuse them.

以上述的想法做为出发,我的设计将会以line buffer做为此种缓冲器的初步设计,之后结合田滨华的loop buffer设计做更进一步的改良,最后再采用藉由指令内容汇流排来传送存取缓冲器中的指令的想法来使得CPU之中的缓冲器可以储存巢状回圈进而提升缓冲器的使用率使得指令内容汇流排的存取次数可以持续地下降。

The thread switch can be done in one CPU cycle.

线程开关可以在一个CPU周期。

173 Notes [4] At the beginning of each instruction cycle, the CPU fetches an instruction from memory.

在每个指令周期的开始,CPU都从内存中取一条指令。

The register-to-register operation execution time is one cycle of the CPU clock.

寄存器和寄存器之间运行的执行时间就是CPU主频的一个周期。

Superscalar refers to a clock cycle of a CPU can execute instructions above.

8超标量是指在一个时钟周期内CPU可以执行一条以上的指令。

A10 as a result of bus slot on the I / O CHRDY with the CPU bus cycle state of a certain degree of contact.

由于总线槽A10上的I/O CHRDY与CPU总线周期的状况有一定的联系。

S A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz.

高性能的A型80C51 CPU的指令规定除外111 ns指令周期时间为222 ns的乘法和除法时,在18 MHz的执行。

of this kind of platform can reduce the working load of processor, quicken data to flow at the same time. I/O quickens a technology to optimize pair of network stack processing above all, undertake trends distinguishs, allocate the cycle of CPU in the light of application, raise chip set and network controller to put an input to output data upcountry with accelerating executive speed; to pass answer ability, the job that reduced processor is laden.

这种平台方法可以减少处理器的工作负载,同时加速数据流。I/O加速技术首先优化对网络堆栈处理,进行动态区分,针对应用分配CPU的周期,以加快执行速度;通过提高芯片组和网络控制器向内存输入输出数据的响应能力,减少了处理器的工作负载。

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