- 更多网络例句与输入总线相关的网络例句 [注：此内容来源于网络，仅供参考]
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VTT, sometimes referred to in the Basic Input/Output System as the FSB Termination Voltage, provides the low level signaling bias needed for the processors, chipsets, and all other devices on the bus to communicate.
VTT，有时在基本输入/输出系统中被称为FSB终结电压，提供处理器、芯片集以及所有其他总线设备通信所必须的低级别信号偏移。
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XC68HC11F1FN Pinout:(1) Power saving driver (2) Built in DA converter accepting 6-bit digital input (for 262,144 colors)(3) Choice of 360 and 324 drive outputs (4) Input data bus at pixel level (5) Choice of output data format: gray scale or binary (6) Eleven reference voltage inputs for producing 10 segment gamma adjustment graph.
XC68HC11F1FN引脚说明：（1）省电驱动程序（2）内置DA转换器接受6位数字输入（为262，144色）（3）选择360和324驱动器输出（4）输入的像素数据总线一级（5）输出数据格式选择：灰阶或二进制（6）11参考生产10段伽玛调整图形电压输入。
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The electrical channel used by the IBM AT and compatible computers to connect the computer's motherboard and peripheral devices, such as memory boards, video controllers, PC card modems, bus mouse boards, hard and floppy disk controllers and serial/parallel input/output devices.
IBM AT以及兼容机使用该电子通道连接计算机母板和外部设备，如存储板、视频控制器、PC卡调制解调器、总线鼠标板、硬盘和软盘控制器以及串行/并行输入/输出设备。
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Ethernet data stream with HTML format and DVB-C data stream with MPEG2 format is inputted in form of ASI and SPI, and send it into FIFO via 74F675A. 5416 packs and encrypts and transfers to DVB-C and Ethernet by time diplex mode. Thereby, data bus access is realized.
HTML格式以太网数据流和MPEG2格式DVB-C数据流以ASI和SPI形式输入，经74F675A串并转换进入FIFO.5416进行打包和加密并以时分复用方式传输DVB-C和以太网数据，实现数据总线访问。
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The PCI-1760U relay actuator and isolated D/I card is a PC add-on card for the PCI bus.
PCI-1762是一款PCI总线的继电器输出及隔离数字量输入板卡。
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The computer system by use of electronic circuits and physical equipment, is almost tangible entities, such as the central processing unit, storage, an external device (input/output devices, I/O devices) and bus, etc.
硬件 计算机系统中所使用的电子线路和物理设备，是看得见、摸得着的实体，如中央处理器、存储器、外部设备（输入输出设备、I／O设备）及总线等。
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The circuit comprises a comparison circuit, a negation gate and a first coincidence gate, wherein the comparison circuit is used to output read screen signals of a storage unit corresponding with bus signals of a second port address, the negation gate is used to inverse the read screen signals of the storage unit which are corresponding with the bus signals of the second port address, one input end of the first coincidence gate receives the read screen signals of the storage unit which are corresponding with the bus signals of the second port address after being inversed, the other input end of the first coincidence gate receives the read enable signals of a second port, and the output end of the first coincidence gate is connected with the read enable end of the second port.
所述电路包括：比较电路，用于输出第二端口地址总线信号对应的存储单元读屏蔽信号；非门，用于对第二端口地址总线信号对应的存储单元读屏蔽信号进行非运算；第一与门，第一与门的一路输入端接收非运算后的第二端口地址总线信号对应的存储单元读屏蔽信号，第一与门的另一路输入端接收第二端口的读使能信号，第一与门的输出端连接第二端口的读使能端。
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Big-Endian ConfigurationA signed byte load expects data on data bus inputs 31 through to 24 if the supplied address is on aword boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on.
大尾段配置阿签署字节负载预计在31日的数据总线输入数据，如果通过向24所提供的地址上的字的边界，数据总线投入23日至16如果它是一个字地址加上一个字节，依此类推。
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Pinout: C High-performance 32-bit RISC Architecture C High-density 16-bit Instruction Set C Leader in MIPS/Watt C Little-endian C Embedded ICE (In-circuit Emulation) 8-, 16- and 32-bit Read and Write Support 256K Bytes of On-chip SRAM C 32-bit Data Bus C Single-clock Cycle Access Fully Programmable External Bus Interface C Maximum External Address Space of 64M Bytes C Up to Eight Chip Selects C Software Programmable 8/16-bit External Data Bus Eight-level Priority, Individually Maskable, Vectored Interrupt Controller C Four External Interrupts, including a High-priority, Low-latency Interrupt Request 32 Programmable I/O Lines Three-channel 16-bit Timer/Counter C Three External Clock Inputs C Two Multi-purpose I/O Pins per Channel Two USARTs C Two Dedicated Peripheral Data Controller Channels per USART Programmable Watchdog Timer Advanced Power-saving Features C CPU and Peripheral Can be Deactivated Individually Fully Static Operation: C 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85C 2.7V to 3.6V I/O Operating Range 1.65V to 1.95V Core Operating Range -40C to +85C Temperature Range Available in 100-lead TQFP Package
M5L8253P-5引脚说明： C型高性能32位RISC架构C高密度以MIPS /瓦C小端C十六位指令集C领袖嵌入式冰8 - 16 -位和32位的读写支持256K的片上SRAM的 32位数据总线C单时钟周期存取字节完全可编程的外部总线接口C最大的外部地址空间的64M字节多达8个C芯片选择C软件可编程8位外部数据总线8级优先级，独立可屏蔽，向量中断控制器C四外部中断，其中包括一个高优先级，低延迟中断要求32个可编程I / O口线三通道16位定时器/计数器C三个外部时钟输入C两多用途I / O引脚每通道2个通用同步C两专用外设数据控制器通道每个USART可编程看门狗定时器先进的节能特性 CPU和外设可停用独立全静态工作中：C 0 Hz至75 MHz的频率范围内的VDDCORE = 1.8，85℃2.7V到3.6VI / O的操作1.65V到1.95V范围核心工作电压范围在- 40C至+85 C温度范围内使用的100引脚TQFP封装
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There are game cards to drive your joysticks.
所有的外设好像都需要通过自己的适配卡来接入总线，例如：高分辨率视频卡、驱动操作杆的游戏卡、驱动话筒的声卡、以及把视频输入到计算机的视频输入卡，类似的设备还有很多
- 更多网络解释与输入总线相关的网络解释 [注：此内容来源于网络，仅供参考]
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AB Address Bus：地址总线
1、 地址总线(AB address bus)地址总线(AB)用来由CPU向存储器(ROM)单元和输入/输出接口发送(传输 地址信息的总线. 由于存储器(ROM)单元和输入/输出接口是不向CPU传输信息的,所以地址总线(AB)是单向传输总线.
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IO bus line：输入输出总线
Inzeria 印卓尔叠层石属 | IO bus line 输入输出总线 | IO channel 输入输出通道
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data input bus：数据输入总线
data input 数据输入 | data input bus 数据输入总线 | data input device 数据输入装置
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DIB Data Input Bus：数据输入总线
DI Dispersion-Increasing 色散增加 | DIB Data Input Bus 数据输入总线 | DIB Device Independent Bitmap 与设备无关位图
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data input bus,DIB：数据输入总线
数据启动控制 data initiated control | 数据输入总线 data input bus,DIB | 数据输入办事员 data input clerk,DIC
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input data bus：输入数据总线
input data 输入数据=>入力データ | input data bus 输入数据总线 | input data check 入力データチェック
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db：数据总线
2、 据总线(DB data bus) 数据总线(DB)用来在CPU与存储器、输入/输出接口和其它电路之间相互传输数据状态和指令. 由于数据可以从CPU传输到内部存储器、输入、输出接口,也可反方向传输到CPU中,所以数据总线(DB)是双向传输的总线,
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DIB DataInputBus：数据输入总线
DI DataInput 数据输入 | DIB DataInputBus 数据输入总线 | DIC DataInputClerk 数据输入员
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FBI FileBusIn：文件输入总线
FBC FileBufferedChannel 全缓冲通道 | FBI FileBusIn 文件输入总线 | FBOE FileBusOut 文件总线输出
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selective channel output bus,SCOB：选择信道输出总线
选择信道输入总线 selective channel input bus,SCIB | 选择信道输出总线 selective channel output bus,SCOB | 选择电路 selective circuit